2010 Cisco and/or its affiliates. All rights reserved.

Cisco Confidential 1 Cisco Confidential 2010 Cisco and/or its affiliates. All rights reserved. 1
ASR1000
Rajnish Kumar (rajnikum@cisco.com)
System Engineer
2010 Cisco and/or its affiliates. All rights reserved. Cisco Confidential 2
2
Introduction
Hardware components
System Architecture & High Availability
Software Architecture, Software Releases
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SERVICE PROVIDER EDGE Routers
ISR Series
7200 Series
ASR 1000
7600 Series
ASR 9000
20-200G / per
System
Broadband
Route Reflector
Distributed PE
Hosted Firewall
IP Sec
SBC/VoIP
40G / Slot
Carrier Ethernet
IP RAN
Mobile Gateways
SBC/VoIP
Broadband
Vidmon
200G / Slot
Carrier Ethernet
IP RAN
L2/L3 VPNs
Vidmon
Managed L2/L3 VPNS
Integrated Security
Application Recognition
Strictly CISCO Confidential
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4
Instant On
Service Delivery
2.5 Gbps to 40Gbps Range - designed today for up to 360 Gbps in the future
Compact,
Powerful Router
Business-Critical
Resiliency
ASR 1002
ASR 1004 ASR 1006
Embedded High-Performance Resilient Services
2.510
Gbps
10-40
Gbps
10-40+
Gbps
Integrated firewall, VPN,
encryption, NBAR, CUBE-
ENT,CUBE-SP
Scalable on-chip service
provisioning through
software licensing
Fully separated control and
forwarding planes
Hardware and software
redundancy
In-service software upgrades
Line-rate performance 2.5G to
100G+ with services enabled
Investment protection with
modular engines, IOS CLI and
SPAs for I/O
Hardware based QoS engine
with 128K queues

ASR 1001
2.5 -
5Gbps
40-360
Gbps
ASR 1013
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BRKARC-2001
Cisco ASR 1000 Series Introduction




SPA Interface Processor (SIP)
Can take Up to 4 HH SPAs
SPA Slots
Re-Uses existing SPAs
Embedded Services Processor
(ESP) 40 Cores with Traffic Manager
Route Processor (RP)
2.66x2 GHz, Up to 16GB DRAM


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BRKARC-2001
6
ASR 1013 Overview
Centralized Forwarding, Hardware
Redundant (RP and ESP) Architecture
RP2 and ESP40, designed to support future
RP and ESP
Expanded I/O capacity - Up to 6 I/O slots
(24 HH-SPAs), 360Gb total
4X40G slots
2X100G slots
Front-to-Back airflow
4 Power Supplies (AC or DC) organized in
2 redundant pairs
Initial target applications:
Broadband, Voice Gateway, DPI, IPSec
aggregation, Carrier Ethernet

ASR 1013
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BRKARC-2001
Chassis Options: ASR1006
RP
ESP
SIP
SPAs
6RU
0

1

0

1

0

1

2

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BRKARC-2001
4RU
Chassis Options: ASR1004
RP
ESP
SIP
SPAs
0/0 0/1
0/2
0/3
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BRKARC-2001
Chassis Options: ASR1002
ESP
SIP
SPAs
2RU
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Supports IOS XE
Common across ASR1000
Ideal for secure/high-end branch, as
Route Reflector, and for managed services
Small footprint (1RU)
Performance of 2.5 Gbps or 5 Gbps
4G & 8G & 16G Memory options
Encryption support of 1.8 Gbps
Integration of ESP, RP, SIP
IO Options
4 built-in GigE ports
1 single-height SPA bay
Integrated daughter card
Models:
With IOS XE 3.2S (NOV10)
ASR1001,ASR1001-2XOC3POS, ASR1001-4XT3
With IOS XE 3.3S (MAR11)
ASR1001-HDD,ASR1001-4X1GE,ASR1001-
8CHT1E!
High Availability with SW redundancy support
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Supports IOS XE
Common across ASR 1000
Performance and Scale
Integrated ESP, RP, and SIP10
ESP throughput can be upgraded from 2.5G to 5G with no
additional HW
Control-Plane performance falls between RP1 and RP2 for
test results
Integrated Services
Same features and services across entire ASR1000 family
Encryption throughput of 1.8G (large packet size, for both
2.5G and 5G options)
High Availability
Dual AC or DC power supplies by default on all units
IOS redundancy
IO Flexibility
One single-height SPA slot that supports same SPAs as rest of
ASR1000 family
Integrated daughter card provides additional IO options in
these models:
ASR1001-2XOC3POS
ASR1001-4XT3
ASR1001-HDD
ASR1001-4X1GE
ASR1001-8CHT1E
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4 Built-in GE ports
Single-Height SPA card slot
Here: 5-port 1GE SPA is plugged in
Management network
interface
NOTE:
This photo depicts ASR1001 without Integrated Daughter Card (IDC)
The arrow ( ) points to location of Integrated Daughter
Card (IDC)
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BRKARC-2001
Route Processor: ASR1000-RP1
Features:
First Generation ASR1000 Route Processor (RP)
1.5GHz PowerPC Processing Complex
Up to 1M v4 / 256K v6 routes
HDD
Enclosure
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BRKARC-2001
Route Processor: ASR1000-RP2
Features:
Second Generation ASR1000 Route Processor (RP)
Dual core 2.66 GHz Intel Xeon Processing Complex
Up to 4M v4, 1M v6 routes
Hot swappable HDD
HDD
Enclosure
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RP1 RP2
CPU General Purpose CPU based on
1.5GHz processor
Dual-Core Processor, 2.66GHz
Memory 2GB default (2x1GB)
4GB maximum (2x2GB)
RP1 with 4GB built in ASR1002
and ASR1002-F
8GB default (4x2GB)
16GB maximum (4x4GB)
Built-in eUSB
bootflash
1GB (8GB on ASR-1002 and
ASR1002-F)
2GB
Storage 40GB HDD & external USB 80GB HDD & external USB
Cisco IOS XE
Operating System
32 bit 64 bit
Chassis Support ASR 1002 (integrated), ASR 1004
and ASR 1006
ASR 1004, ASR 1006 and ASR 1013
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BRKARC-2001
Forwarding Processor: ASR1000-ESP10
Features:
10 Gbps Performance
QFP (QuantumFlow Processor)
800MHz ESP CPU Processing Complex for Control

Cisco
QuantumFlow
Processor
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BRKARC-2001
Forwarding Processor: ASR1000-ESP20
Features:
20 Gbps Performance
QFP (QuantumFlow Processor)
1.2 GHz ESP CPU Processing Complex for Control

Cisco
QuantumFlow
Processor
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BRKARC-2001
18
Centralized, programmable forwarding
engine (i.e. QFP subsystem (PPE) and
crypto engine) providing full-packet
processing
Packet buffering and queuing/scheduling
(BQS)
Increases BW to provide 40G throughput
11Gbps crypto BW throughput
Interconnect providing data path links (ESI)
to/from other cards over midplane
Support up to two 23 Gbps ESI links to
each SIP slot (1 x 11G or 2 x 23G)
FECP CPU (1.86GHz dual core CPU with
8GB memory) managing QFP, crypto
device, midplane links, etc
ASR1000-ESP40
QFP
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ESP-2.5G ESP-5G ESP-10G ESP-20G ESP-40G
System Bandwidth 2.5Gbps 5Gbps 10Gbps 20Gbps 40Gbps
Performance 3Mpps 8Mpps 17Mpps 24Mpps 24Mpps
# of Processors 10 20 40 40 40
Clock Rate 900 Mhz 900 Mhz 900 Mhz 1.2 GHz 1.2 GHz
Crypto Engine BW
(1400 bytes)
1Gbps 1.8Gbps 4.4Gbps 8.5Gbps 11Gbps
QFP Resource
Memory
256MB 256MB 512MB 1GB 1GB
Packet Buffer 64MB 64MB 128MB 256MB 256MB
Control CPU 800 MHz 800 MHz 800 MHz 1.2 GHz 1.8 GHz
Control Memory 1GB 1GB 2GB 4GB 8GB
TCAM 10Mb 10Mb 10Mb 40Mb 40Mb
Chassis Support
ASR 1001
(Integrated)
ASR 1001
(integrated),
ASR1002
ASR 1002, 1004,
1006
ASR 1004,
1006
ASR 1006,
1013
Based on Quantum Flow Processor (QFP)
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BRKARC-2001
SPA Interface Processor: ASR1000-SIP10
Features:
First Generation ASR1000 SIP
10 Gbps Aggregate Performance
800MHz SIP10 CPU Processing Complex for Control

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BRKARC-2001
21
ASR1000-SIP40
Physical termination of SPA (compatible with
existing and future SPAs)
40Gbps aggregate throughput, can also operate
in 10 Gbps mode (SIP10 mode)
Capable of connecting to all previous ESPs using
two ESI modes: 1x10G and 2x20G
Does not participate in forwarding
Physical Interface QoS
Ingress packet classification high/low
128MB of ingress buffer, strict priority
scheduling
8MB egress buffer internal (48 dual priority or
96 single priority queues), also split into two
halves, each dedicated to two SPAs
Capture stats on dropped packets
Network clock distribution to SPAs, reference
selection from SPAs
IOCP manages Midplane links, SPA OIR, SPA
drivers
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ASR1000-SIP10 ASR1000-SIP40
Bandwidth 10G 40G
Ingress Buffering 128MB 128MB
Egress Buffering 8MB 8MB
ESI Frequency 3.125GHz 6.25GHz or 3.125GHz
Bandwidth per ESI Link 11Gbps 23Gbps
ESI Links used 1 1 or 2
Total Bandwidth 11Gbps 23Gbps/46Gbps
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SPAs currently supported on other Cisco platforms
will also be supported on the ASR 1000
POS
OC3
OC12
OC48
Clear Channel
T3/E3
Channelized
T1/E1
T3
STM1, STM4
Ethernet
FE
GE
10GE
Serial
12 in 1
ATM
OC3
OC12
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Ethernet SPA
SPA-4X1FE-TX-V2
SPA-8X1FE-TX-V2
SPA-2X1GE-V2
SPA-5X1GE-V2
SPA-8X1GE-V2
SPA-10XGE-V2
SPA-1X10GE-L-V2
Optics
SFP-GE-S
SFP-GE-L
SFP-GE-Z
SFP-GE-T
CWDM
XFP-10GLR-OC192SR
XFP-10GER-OC192IR
XFP-10GZR-OC192LR
GLC-GE-100FX
GLC-BX-U
GLC-BX-D
Channelized
SPA-8XCHT1/E1
SPA-2XCT3/DS0
SPA-3XCT3/DS0
SPA-1XCHSTM1/OC3
ATM SPA
SPA-1XOC3-ATM-V2
SPA-3XOC3-ATM-V2
SPA-1XOC12-ATM-V2
Optics
SFP-OC3-MM
SFP-OC3-SR
SFP-OC3-IR1
SFP-OC3-LR1
SFP-OC3-LR2
SFP-OC12-MM
SFP-OC12-SR
SFP-OC12-IR1
SFP-OC12-LR1
SFP-OC12-LR2
SFP-OC48-SR
SFP-OC48-IR1
SFP-OC48-LR2
XFP-10GLR-OC192SR
XFP-10GER-OC192IR
XFP-10GZR-OC192LR
Serial / POS
SPA-4XT-Serial
SPA-2XT3/E3
SPA-4XT3/E3
SPA-2XOC3-POS
SPA-4XOC3-POS
SPA-8XOC3-POS
SPA-1XOC12-POS
SPA-2XOC12-POS
SPA-4XOC12-POS
SPA-8XOC12-POS
SPA-1XOC48POS/RPR (POS mode)
SPA-2XOC48POS/RPR (POS mode)
SPA-4XOC48POS/RPR (POS mode)
SPA-OC192POS-XFP (POS Mode)
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ASR1001 ASR 1002 ASR 1004 ASR 1006 ASR 1013
SPA Slots 1-slot 3-slot 8-slot 12-slot 24-slot
ESP Slots Integrated
Integrated 1 2 2
SIP slots Integrated Integrated 2 3 6
IOS Redundancy Software Software Software Hardware Hardware
Built-in GE 4 4 N/A N/A N/A
Height 1.75 (1RU) 3.5 (2RU) 7 (4RU) 10.5 (6RU) 22.7 (13RU)
Bandwidth 2.5 to 5 Gbps 5 to 10 Gbps 10 to 40 Gbps
40 Gbps as of
3.2S
10 to 40 Gbps 40+ Gbps
Maximum output
Power
400W 470W 765W 1275W 3200W
Airflow Front to back Front to back Front to back Front to back Front to back
Integrated I/O
Daughtercard
1
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ASR1001 ASR1002 ASR1004 ASR1006 ASR1013
Chassis
Scalable to 5 Gbps via.
Software activated
license.
Four built-in GE ports.
Software redundancy
Scalable to 10 Gbps.
Four built-in GE ports.
Software redundancy.
Scalable to 40 Gbps+
Software redundancy.
Scalable to 40 Gbps+
Hardware redundancy.
Scalable to 40Gbps+
Hardware redundancy
Embedded
Services
Processors
Integrated Software
Upgradeable
ASR1001-ESP2.5/5
(single)
ASR1000-ESP5
(single)
ASR1000-ESP10
(single)
ASR1000-ESP10
(redundant)
NA
ASR1000-ESP10
(single)
ASR1000-ESP20
(single)
ASR1000-ESP20
(redundant)

NA


NA

NA
ASR1000-ESP40
(redundant)
ASR1000-ESP40
(redundant)
Route Processor
Integrated
ASR1001-RP
(single)
Integrated
ASR1000-RP1
(single)
ASR1000-RP1
(single)
ASR1000-RP1
(redundant)
NA
ASR1000-RP2
(single)
ASR1000-RP2
(redundant)
ASR1000-RP2
(redundant)
SPA Interface
Processor
Integrated Integrated ASR1000-SIP10
ASR1000-SIP10 ASR1000-SIP10
ASR1000-SIP40 ASR1000-SIP40
SPA Slots 1 (single height) 3 (single height) 8 (single height) 12 (single height) 24 (single height)
Integrated I/O
Daughterboard
1 NA NA NA NA
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RP (Route Processor)
Handles control plane traffic
Manages system
ESP (Embedded Services Processor)
Handles forwarding plane traffic
SPA Interface Processor
Shared Port Adapters provide
interface connectivity
Centralized Forwarding Architecture
All traffic flows through the active
ESP, standby is synchronized with all
flow state with a dedicated 10Gbps
link
Distributed Control Architecture
All major system components have a
powerful control processor
dedicated
for control and management planes

Route
Processor
(standby)
RP
Interconn.
Forwarding
Processor
(active)
FECP
Interconn.
QFP
subsys-
tem
Crypto
assist
Forwarding
Processor
(standby)
FECP
Interconn.
QFP
subsys-
tem
Crypto
assist
SPA SPA
IOCP
SPA
Agg.

Interconn.
SPA SPA
IOCP
SPA
Agg.

Interconn.
SPA SPA
IOCP
SPA
Agg.

Interconn.
Midplane
Route
Processor
(active)
RP
Interconn.
SPA-SPI, 11.2Gbps
Hypertransport, 10Gbps
ESI, (Enhanced Serdes Interface) 11.5Gbps
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5 year design
Massively parallel, 40 multi-threaded cores
QFP Architecture designed to scale to >100Gbit/sec
160 processes available to handle traffic
High-priority traffic is prioritised
Packet replication capabilities for Lawful Intercept
Full visibility of entire L2 frame
Latency: tens of microseconds with features enabled
Interfaces on-chip for external cryptographic engine
Current generation QFP is capable of 20Gbit/sec, 32Mpps
processing
Cisco QFP Sun Ultrasparc T2 Intel Core 2 Mobile
U7600
Total number
processes (cores x
threads)
160 64 2
Power per process
0.51W 1.01W 5W
Scalable traffic
management
128k queues None None

Cisco QFP
Cisco QFP Traffic Manager
ASR 1000 Series Innovations
Cisco QuantumFlow Processor
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ASR1000 has a passive back-plane. The thruput of the system is determined by the type of ESP and SIP
used in the system.
ESP bandwidth denotes the total output bandwidth of the system, regardless of the direction.
High priority traffic (as long as it is not over-subscribed - Example: <=10G for ESP-10G) will not be affected
by this bandwidth limit
ESP-10G Examples:
5G 5G
5G 5G
ASR 1000
5G Unicast in each direction
Total Output bandwidth 5+5=10
1G 8G
2G 2G
1G Multicast with 8X replication in one direction
2G unicast in the other direction
Total Output bandwidth 8+2=10G
5G 5G
6G 6G
5G Unicast in one direction & 6G Unicast
in the other direction
Total output bandwidth (5+6=11) exceeds
10G; Only 10G will go through
1G 10G
1G 1G
1G Multicast with 10X replication in one direction
1G Unicast in the other direction
Total bandwidth (10+1=11) exceeds 10G; only 10G
will go through
ASR 1000
ASR 1000 ASR 1000
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ASR 1000 leverages Cisco IOS HA infrastructure NSF/SSO,
ISSU
1+1 redundancy option for RP and ESP
Active and standby
No load balancing
RPs are separate from ESPs
Switchover of ESP does not result in switchover of RP
Switchover of RP/IOS does not result in switchover of ESP
Single RP may be configured with dual IOS for SW redundancy
(single RP only)
No redundancy for SIP or other I/O cards
SPA plugs into a single SIP
Protection against SPA or SIP failure is via APS or Y-cable
redundancy feature (Future: requires SPA support)
2010 Cisco and/or its affiliates. All rights reserved. Cisco Confidential 35
Active
Forwarding
Processor
Active
Route
Processor
Standby
Route
Processor
Standby
Forwarding
Processor
SPA Interface Processor
SPA SPA
SPA SPA
SPA Interface Processor
SPA SPA
SPA SPA
SPA Interface Processor
SPA SPA
SPA SPA
Zero
Packet
Loss
RP fails
HW or SW
Standby
Becomes
Active
Separate and independent internal communication link for control plane (GE)
2010 Cisco and/or its affiliates. All rights reserved. Cisco Confidential 36
Active
Forwarding
Processor
Active
Route
Processor
Standby
Route
Processor
Standby
Forwarding
Processor
SPA Interface Processor SPA Interface Processor SPA Interface Processor
SPA SPA SPA SPA SPA SPA
SPA SPA
SPA SPA SPA SPA

ESP fails SW or HW
Standby
Becomes Active
Minimal
Data
Interruption
All packets processed by QFP for forwarding
Separate and Independent links for Data Plane communication (ESI 11.5G)
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Enhanced Services
Processor
Route Processor
SPA Interface Processor
Control Messaging
Kernel Kernel
Kernel
QFP
Client/Driver
IOS XE = IOS + IOS XE Middleware +
Platform Software
Operational Consistency - same look and
feel as IOS Router
IOS runs as its own Linux process for
control plane (Routing, SNMP, CLI etc). 32bit
and 64bit options.
Linux kernel with multiple processes
running in protected memory for
Fault containment
Re-startability
ISSU of individual SW packages
ASR 1000 HA Innovations
Zero-packet-loss RP Failover (ASR1006)
<50ms ESP Failover
Software Redundancy (ASR1001/2/4)
Chassis
Manager
Forwarding
Manager
SPA
Driver
SPA
Driver
SPA
Driver
SPA
Driver
Forwarding
Manager
Chassis
Manager
IOS
12.2SR
(Active)
IOS XE Middleware
Chassis
Manager
IOS
12.2SR
(Standby)
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BRKARC-2001
An IOS XE InnovationDual Cisco IOS
An option to run dual
IOS images on single
RP HW for 2/4 RU
chassis results in zero
service disruption
during IOS upgrades
Failover of IOS
instance or RP doesnt
cause service impact
to IOS FW or NAT
Route Processor
Embedded Services
Processor
Kernel
QFP
Forwarding
Manager
Chassis
Manager
Kernel
Chassis
Manager
Interface
Manager
Forwarding
Manager
IOS
12.2XN
(Standby)
IOS
12.2XN
(Active)
IOS XE Middleware
SPA Interface
Processor
Kernel
SPA
Driver
SPA
Driver
SPA
Driver
SPA
Driver
Interface
Manager
Chassis
Manager
Control Messaging
2010 Cisco and/or its affiliates. All rights reserved. Cisco Confidential 43
Thank you.