CHAPTER 5. Memory Element: Electrical Engineering Department PTSB

CHAPTER 5.
Memory Element
Electrical Engineering Department
PTSB
EC303 COMPUTER ARCHITECTURE & ORGANIZATION
Learning Outcomes

After learning of this chapter, student should be
able:-
To know the computer memory organization
To understand Virtual Memory Organization
To understand cache memory
To understand decoder
To realize connecting memory chips to computer
bus

2
Brainstorming
3
4
Computer Memory Organization
Memory
5
Main memory consists of a number
of storage locations, each of which is
identified by a unique address
The ability of the CPU to identify
each location is known as its
addressability
Each location stores a word i.e. the
number of bits that can be processed
by the CPU in a single operation.
Word length may be typically 16, 24,
32 or as many as 64 bits.
A large word length improves system
performance, though may be less
efficient on occasions when the full word
length is not used
Block Diagram of Memory
An M-bit data value can be read or written at each unique N-bit address
Read operation- take data out of the specified address in the memory
Write operation put data into a specified address in memory
6
Memory
2
N
words
(M-bit per word)
Read/Write
Chip Select
(Chip Enable)
M-bit Data Output
(for Read/Write)
M
Example: Byte-addressable
2MB memory
M = 8 (because of byte-
addressability)
N = 21 (1 word = 8-bit)
N-bit
address lines
N

7

8

9
10
D7
D2
D1
D0
A10
A8
A7
A0
2K x 8
R/W CS
RAM CHIP
Design a 2K x 8 memory chips
0 = Write
1 = Read
CS = CHIP SELECT
CS = 0 enables the
output buffers
Describe the buses line to interface
memory
In computer architecture, a bus is a subsystem that transfers data between
components inside a computer, or between computers.

How the RAM chip works?
a) Data bus -Carry information
b) Address bus- Determine where it
should be sent
c) Control bus - Determine its operation

12
OPERATION OF P SYSTEM (Fetch &
Execute Cycles cont)
Read Cycle :
- CPU sends a signal via control bus. If the bus
is busy, CPU is put on Wait state.
- If the bus is free, CPU will place instruction
address on the address bus.
- This address will be decoded or translated by
the circuitry in the memory or I/O interface.
- Finally the data at the specific address is
obtained and is placed on the data bus.
13
OPERATION OF COMPUTER SYSTEM
Fetch & Execute Cycles Cont..
14

15
Write cycles :
- Write cycle enables CPU sends data to the
memory or I/O devices.
- CPU will send a signal (request to write) to the
control bus.
- If the data bus is free, the data is placed on the
data bus, whereas the location address will be
placed on the address bus.
- CPU will then send the data to the destination
with respect to the address.

16
17
OUTCOME :
a. Design an interface chip circuit for an 8-word 3-
bit RAM chip.
b. Manipulate the circuit (from a) to design layout
circuit for adding memory to a bus using
decoder
c. Define function of decoder.
d. Illustrate the circuit of a four-output decoder
and parallel decoder.
18
19
RAM CHIP
Design a 8-word 3 bit RAM chip ?
D2
D1
D0
8 X 3
R/W CS
A0
Q & A
20

How to design a 1Mx8 computer system
using 1Mx4 memory chips
Building Memory in Hierarchy
Design a 1Mx8 using 1Mx4 memory chips
21
D3
D2
D1
D0
A19
A18
A17
A0
1Mx4
R/W CS
D7
D6
D5
D4
A19
A18
1Mx4
R/W CS
A17
A0
CS
Prof. Sean Lees Slide, Georgia Tech
Q & A
22

How to design a
2Mx4 using 1Mx4 memory chips
1) How many chip ?
Chip needed = system needed
chip used
2) Calculate the address line for chip used
3) Calculate the address line for system
4) Decide the decoder needed

23
A19
A18
A17
A0
1Mx4
R/W CS
A19
A18
A17
A0
1Mx4
R/W CS
A20
1-to-2
Decoder
CS
1
0
D3
D2
D1
D0
Q & A
24

How to design a
64Kx8 computer system
using 16Kx4 memory chips

1) How many chip ?
Chip needed = system needed
chip used
2) Calculate the address line for chip used
3) Calculate the address line for system
4) Decide the decoder needed
5) Calculate the data lines for chip and system

Design a 64Kx8 using 16Kx4 memory chips
25
A13
A12
A11
A0
16Kx4
CS R/W
A13
A12
A11
A0
16Kx4
CS R/W
A13
A12
A11
A0
16Kx4
CS R/W
A13
A12
A11
A0
16Kx4
CS R/W
D7
D6
D5
D4
D3
D2
D1
D0
A13
A12
A11
A0
A14
2-to-4
Decoder
CS
1
0
A15
2
3
Memory Organization Example
26
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
0
1
2
3
D7 D6 D5 D4 D3 D2 D1 D0
4 words x 8 bits
2-to-4

Decoder
A0
A1
CS
Chip Select
Wordline (WL)
BitLine
Modified from Prof Sean Lees Slide, Georgia Tech
How to Address Memory
27
0
1
2
3
D7 D6 D5 D4 D3 D2 D1 D0
2-to-4

Decoder
A0=1
A1=0
Access address = 0x1
CS
Chip Select=1
4 words x 8 bits
28
Decoder
Decoder
A decoder is a device which does the reverse of an encoder, undoing the
encoding so that the original information can be retrieved.

Four-output decoder and a parallel decoder
Determine the digital circuit in a tree-type
decoding network with 16 output lines
The first stage is a 2-to-4-line decoder. A new variable is introduced in each successive stage; it or
its inverse becomes one input to each of the two-input AND gates in this stage. The second input to
each AND gate comes from the preceding stage. For example, one of the outputs of the second
stage will be AB'C. This will result in two outputs from the next stage, AB'CD and AB'CD'. This design
does avoid the fan-out problem in the early stages but not in the later stages. Nevertheless, the
problem exists only for the variables introduced in those stages.
A balanced multiplicative decoder
network
Requires the minimum number of diodes
This decoder circuit is the fastest and most
regular.

33
Computer Memory Hierarchy
Storage Hierarchies :
Computer data storage often called storage or memory, refers to computer
components and recording media that retain digital data. Data storage is one of
the core functions and fundamental components of computers.
PRIMARY STORAGE

Primary storage (or main memory or internal memory), often referred to simply as memory, is
the only one directly accessible to the CPU. The CPU continuously reads instructions stored there and
executes them as required. Any data actively operated on is also stored there in uniform manner.

RAM:
Processor registers are located inside the processor. Each register typically holds a word of data
(often 32 or 64 bits). CPU instructions instruct the arithmetic and logic unit to perform various
calculations or other operations on this data (or with the help of it). Registers are the fastest of all
forms of computer data storage.

Processor cache is an intermediate stage between ultra-fast registers and much slower main
memory. It's introduced solely to increase performance of the computer. Most actively used
information in the main memory is just duplicated in the cache memory, which is faster, but of much
lesser capacity.

Main memory is directly or indirectly connected to the central processing unit via a memory bus. It is
actually two buses ): an address bus and a data bus. The CPU firstly sends a number through an
address bus, a number called memory address, that indicates the desired location of data. Then it
reads or writes the data itself using the data bus.

SECONDARY STORAGE

Secondary storage (also known as external memory or auxiliary storage), differs from primary
storage in that it is not directly accessible by the CPU. The computer usually uses its input/output
channels to access secondary storage and transfers the desired data using intermediate area in
primary storage. Secondary storage does not lose the data when the device is powered downit is
non-volatile.
Example: Flash drive, CD and DVD drives, floppy disks, punch cards.

TERTIARY STORAGE
Tertiary storage or tertiary memory, provides a third level of storage. Typically it involves a
robotic mechanism which will mount (insert) and dismount removable mass storage media into a
storage device according to the system's demands; this data is often copied to secondary storage
before use.
Example: useful for extraordinarily large data stores, accessed without human operators(robotic
arms). Typical examples include tape libraries and optical jukeboxes.

Off-line storage
Off-line storage is a computer data storage on a medium or a device that is not under the control
of a processing unit. The medium is recorded, usually in a secondary or tertiary storage device, and
then physically removed or disconnected. It must be inserted or connected by a human operator
before a computer can access it again. Unlike tertiary storage, it cannot be accessed without human
interaction.
Example : Optical discs and flash memory devices
Memory Devices Hierarchy
37
Memory Hierarchy
Typical Memory Parameters
As you can see in the diagram above, the CPU accesses memory
according to a distinct hierarchy. Whether it comes from permanent
storage (the hard drive) or input (the keyboard), most data goes in
random access memory (RAM) first.

The CPU then stores pieces of data it will need to access, often in a
cache, and maintains certain special instructions in the register.
We'll talk about cache and registers later.

All of the components in your computer, such as the CPU, the hard
drive and the operating system, work together as a team, and
memory is one of the most essential parts of this team.

From the moment you turn your computer on until the time you
shut it down, your CPU is constantly using memory
38
39
The most important parameters of a memory
system are:
Capacity - the maximum number of units of data that
it can store.
Access time - the time taken to access the data in
memory.
Data transfer rate - the number of bits per second at
which data can be read.
Cycle time - A measure of low often a memory can be
accessed.
Cost - Usually expressed in terms of dollars per bit.
Mainly the computer memory system is divided
into two:
Internal memory
External memory
40
Virtual Memory Organization
Virtual Memory
Solves problem of limited memory space
Creates the illusion that more memory exists
than is available in system
Two types of addresses in virtual memory
systems
Virtual addresses Referenced by processes
Physical addresses- Describes locations in main
memory
Memory management unit (MMU)
Translates virtual addresses to physical address
41
42
Virtual Memory System
Processor
MMU
Cache
Main Memory
Disk
Storage
Virtual address
Physical address
Data
/ instructions
Physical address
Transfer it
reference not in
physical
memory
Controlled
by
processor

Controlled
by
Operating
System

Data
/ instructions
The address space needed and seen by
programs is usually much larger than available
main memory
Only one part of the program fits into main
memory, the rest stored on secondary memory
(hard disk)
In order to be executed or data to be accessed,
a certain segment of the program has to be first
loaded into main memory, in this case it has to
replace another segment already in memory.
43
Movement of programs and data, between main
memory and secondary storage, is performed
automatically by the operating system. These
techniques are called virtual memory
techniques.
The binary address issued by the processor is a
virtual address, it considers a virtual address
space, mush larger than the physical one
available in main memory
44
If a virtual address refers to a part of program
or data that is currently in the physical memory
(cache, main memory), then the appropriate
location is accessed immediately using the
respective physical address, if this is not the
case , the respective program/data has to be
transferred first secondary memory.
A special hardware unit, Memory Management
Unit (MMU), translate virtual address into
physical ones.
45
TWO common approaches of Virtual
Memory Organization
Two common approaches of Virtual Memory
Linear Virtual Memory
Segmented Virtual Memory
46
How Virtual Memory is Organized?
Virtual memory is organized by either:-
paging or
segmentation
47
Virtual Memory Organization-Paging
The virtual programme space (instruction+data)
is divided into equal, fixed-size chunks called
pages.
Physical main memory is organized as a
sequence of frames, a page can be assigned to
an available frame in order to be stored (page
size = frame size)
The page is the basic unit of information which
is moved between main memory and disk by the
virtual memory system
Paging
49
Pages on disk
Frames in main memory
Pages
The program consists of a large amount of
pages which are stored on disk, at any one time,
only a few pages have to be stored in main
memory.
The OS is responsible for loading/ replacing
pages so that the number of page faults is
minimized
We have a page fault when the CPU refers to a
location in a page which is not in main memory,
this page has then to be loaded and, if there is
no available frame, it has to replace a page
which previously was in memory
50
Paging
paging
Virtual memory space : 2 GB
(31 address line, 2^31=2GB)
Physical memory space : 16 MB
(24 address line, 2^24=16MB)
Page length:
2^11 = 2KB
51
paging
Total number of pages
Virtual memory space = 2^31 = 2^20 = 1MB
Page length 2^11
Total number of frames
Physical memory space = 2^24 = 2^13 = 8k
Page length 2^11

52
Pages on disk= 20
Frames in main memory = 13
Pages
Paging
Accessing a word in memory involves the
translation of a virtual address into a physical
one
- Virtual address :page number + offset
- Physical address : frame number + offset
Paging
54
55
Virtual memory is divided into fixed-size blocks
called pages
typically a few kilobytes
should be a natural unit of transfer to/from disk
Page replacement
LRU, MRU, Clock etc
Page placement
Fully associative - efficient
Segmentation
Supports user view of memory.
Virtual memory is divided into variable
length regions called segments
Virtual address consists of a segment
number and a segment offset
<segment-number, offset>
Segmentation
Very few systems use the concept of segmentation for
implementing virtual memory.
In segmentation memory is divided in variable size segments.
Segment number and an offset within the segment together
form a virtual address.
If a processor wants a particular data item it first looks up for its
segment number in a segment table to find a segment
descriptor.
Segment descriptor gives information whether the offset within
the segment is less than the length of the segment and if it isn't
an interrupt is generated to notify that the segment is found.
If the processor is unable to find the segment in the main
memory it generates a hardware interrupt prompting the
operating system to swap in the segment.
The operating system then searches for the segments that were
not in use for a long time and swaps them out of main memory
in order to make space for the new segments to be read in.
57
Contrast Paging Vs Segmentation
58
Paging:
Block replacement easy
Fixed-length blocks

Segmentation:
Block replacement hard
Variable-length blocks
Need to find
contiguous, variable-
sized, unused part of
main memory

59
Paging:
Invisible to application
programmer
No external fragmentation
There is internal
fragmentation
Unused portion of page
Units of code and data
are broken up into
separate pages
Segmentation:
Visible to application
programmer
No internal
fragmentation
Unused pieces of main
memory
There is external
fragmentation
Keeps blocks of code or
data as single units

60
Cache Memory
Cache- Introduction
61
Small amount of fast memory
Sits between normal main memory and CPU
May be located on CPU chip or module

Small capacity, fast
Large capacity, slow
Is an intermediate buffer between CPU and main
memory.
Objective :- to reduce the CPU waiting time
during the main memory accesses.
Without cache memory, every main memory
access results in delay in instruction processing.
Due to main memory access time is higher than
processor clock period.
High speed CPUs time wasted during memory
access (instruction fetch, operand fetch or result
storing)
To minimize the waiting time for the CPU, a small
but fast memory is introduced as a cache
buffer between main memory and CPU
62
A portion of program and data is brought into the cache
memory in advance.
The cache controller keeps track of locations of the main
memory which are copied In cache memory
When CPU needs for instruction or operand, it receives
from the cache memory (if available) instead of
accessing the main memory.
Thus the memory access is fast because the slow main
memory appears as a fast memory.
The cache memory capacity is very small compared to
main memory but the speed is several times better than
main memory.
Transfer between the CPU and cache memory usually
one word at a time.
The cache memory usually can be physically with processor
IC as internal cache, also known as on-chip cache.

63
Cache Memory Structure

64
Cache consists of C-lines.
Each line contains K words and a tag of a few bits.
The number of words in the line referred as line size.
Tag- a portion of main memory address.
Each line includes a tag identifies which particular block
is currently being stored.

Cache Operation - Overview
CPU requests contents of memory location
Check cache for this data
If present, get from cache (fast)
If not present, read required block from main
memory to cache
Then deliver from cache to CPU
Cache includes tags to identify which block of
main memory is in each cache slot

65
Typical Cache Organization

66
Direct mapping cache example
In a direct mapping cache with a capacity of 16
KB and a line length of 32 bytes, determine the
following;

i) How many bits are used to determine the
byte that a memory operation references within
the cache line?

ii) How many bits are used to select the line in
the cache that may contain the data.

68
Direct mapping
Each block of main memory maps to only one
cache line
i.e. if a block is in cache, it must be in one
specific place
Address is in two parts
Least Significant w bits identify unique word
Most Significant s bits specify one memory
block
The MSBs are split into a cache line field r and
a tag of s-r (most significant)

69
70
Direct Mapping Address Structure : Example
Tag Line or Slot Word
s-r
r w
EXAMPLE : TAG=8, LINE = 14, WORD=2
24 bit address
2 bit word identifier (4 byte block)
22 bit block identifier
8 bit tag (=22-14)
14 bit slot or line
No two blocks in the same line have the same Tag field
Check contents of cache by finding line and checking
Tag
71
Direct Mapping Cache Line Table
Cache line Main Memory blocks held
0 0, m, 2m, 3m2s-m
1 1,m+1, 2m+12s-m+1
. .
. .
. .
m-1 m-1, 2m-1,3m-12s-1
72
Direct Mapping Cache Organization
73
Direct
Mapping
Example
74
Connecting Memory Chips To Computer Bus
Describe the buses line to interface
memory
In computer architecture, a bus is a subsystem that transfers data between
components inside a computer, or between computers.

How the RAM chip works?
a) Data bus -Carry information
b) Address bus- Determine where it
should be sent
c) Control bus - Determine its operation
Read cycle for a RAM chip
Read Bus Cycle: Describes the operations carried out by the processor when a
memory read is executed.

Step of Read Bus Cycle:
Processor initiates a read bus cycle by floating the address of the memory location on
the address lines.
Once the address lines are stable, the processor asserts the address strobe signal on
the bus. The address strobe signals the validity of the address lines.
Processor then sets the Read/Write* signal to high, i.e. read.
Now the processor asserts the data strobe signal. This signals to the memory that the
processor is ready to read data.
The memory subsystem decodes the address and places the data on the data lines.
The memory subsystem then asserts the data acknowledge signal. This signals to the
processor that valid data can now be latched in.
Processor latches in the data and negates the data strobe. This signals to the memory
that the data has been latched by the processor.
Processor also negates the address strobe signal.
Memory subsystem now negates the data acknowledgement signal. This signals the
end of the read bus cycle.

Read cycle
Write Bus Cycle: Sequence of operations in memory write is described here.

Step of Write Bus Cycle:
Processor initiates a write bus cycle by floating the address of the memory location
on the address lines.
Once the address lines are stable, the processor asserts the address strobe signal on
the bus. The address strobe signals the validity of the address lines.
Processor then sets the Read/Write* signal to low, i.e. write.
The processor then places the data on the data lines.
Now the processor asserts the data strobe signal. This signals to the memory that the
processor has valid data for the memory write operation.
The memory subsystem decodes the address and writes the data into the addressed
memory location.
The memory subsystem then asserts the data acknowledge signal. This signals to the
processor that data has been written to the memory.
Then the processor negates the data strobe, signaling that the data is no longer valid.
Processor also negates the address strobe signal.
Memory subsystem now negates the data acknowledgement signal, signaling an end
to the write bus cycle.

Write cycle for a RAM chip
How CPU read from memory and
write to memory
The computer loads the operating system (OS) from the hard
drive into the system's RAM. Generally, the critical parts of
the operating system are maintained in RAM as long as the
computer is on.
This allows the CPU to have immediate access to the
operating system, which enhances the performance and
functionality of the overall system.
When you open an application, it is loaded into RAM. To
conserve RAM usage, many applications load only the
essential parts of the program initially and then load other
pieces as needed.
After an application is loaded, any files that are opened for
use in that application are loaded into RAM.

79
When you save a file and close the application, the file is
written to the specified storage device, and then it and the
application are purged from RAM.
In the list above, every time something is loaded or opened, it
is placed into RAM. This simply means that it has been put in
the computer's temporary storage area so that the CPU can
access that information more easily.
The CPU requests the data it needs from RAM, processes it
and writes new data back to RAM in a continuous cycle. In
most computers, this shuffling of data between the CPU and
RAM happens millions of times every second.
When an application is closed, it and any accompanying files
are usually purged (deleted) from RAM to make room for new
data. If the changed files are not saved to a permanent
storage device before being purged, they are lost.

80
Static Random Access Memory (SRAM)
Typically each bit is implemented with 6 transistors (6T)

Read operation
The bitline and its inverse are precharged to Vdd (1)
Then set Wordline (WL) high
Depending on the value stored, either bitline or ~bitline goes low

Write operation
Put the new value on Bitline and its inverse on ~Bitline
Then set the Wordline to high

81
BitLine
BitLine
Wordline (WL)
Dynamic Random Access Memory (DRAM)
1-transistor DRAM cell

Write operation
Put value on bitline and then set WL=1

Read operation
Precharge bitline to Vdd (1)
Assert WL to 1

Storage decays, thus requires periodic refreshing
Read bitline data and write it periodically to keep the value in the memory cell
82
Bitline
Wordline (WL)
Memory Description
Capacity of a memory is described as
# addresses x Word size

Examples:
83
Memory # of addr # of data lines # of addr lines # of total bytes
1M x 8 1,048,576 8 20 1 MB
2M x 4 2,097,152 4 21 1 MB
1K x 4 1024 4 10 512 B
4M x 32 4,194,304 32 22 16 MB
16K x 64 16,384 64 14 128 KB
Example
84
Memory with 2 Decoders
85
0
1
2
3
8 words x 4 bits
2-to-4

Row
Decoder
A1
A2
1-to-2 Column Decoder
D0
D1
D2
D3
Tristate
Buffer
(read)
0 1
A0
CS
Chip Select
CS
Read Operation
86
0
1
2
3
8 words x 4 bits
A1
A2
D0
D1
D2
D3
0 1
A0 = 0
CS
Chip Select
CS
Rd/Wr = 0
2-to-4

Row
Decoder
Write Operation
87
0
1
2
3
A1
A2
D0
D1
D2
D3
0 1
A0 = 1
CS
Chip Select
CS
Rd/Wr = 1
8 words x 4 bits
2-to-4

Row
Decoder
88
D3
D2
D1
D0
A19
A18
A17
A0
1Mx4
R/W CS
D7
D6
D5
D4
A19
A18
1Mx4
R/W CS
A17
A0
CS
89
A19
A18
A17
A0
1Mx4
R/W CS
A19
A18
A17
A0
1Mx4
R/W CS
A20
1-to-2
Decoder
CS
1
0
D3
D2
D1
D0
90
A19
A18
A17
A0
1Mx4
CS R/W
A19
A18
A17
A0
1Mx4
CS R/W
A19
A18
A17
A0
1Mx4
CS R/W
A19
A18
A17
A0
1Mx4
CS R/W
D7
D6
D5
D4
D3
D2
D1
D0
A19
A18
A17
A0
A20
1-to-2
Decoder
CS
1
0
Read-Only Memory (ROM)
Non-volatile memory
Permanent binary information is stored
Power off does not erase information stored
91
ROM
2
k
words
(N-bit per word)
N-bit Data Output
K-bit address
lines
N K
32 x 8 (32 words x 8 bits) ROM
92
32 X 8 ROM
8 5
0
1
2
3
28
29
30
31
D7 D6 D5 D4 D3 D2 D1 D0
A4
A3
A2
A1
A0
5-to-32

Decoder
Each
represents
32 wires
To read the cell, the bitline is weakly pulled HIGH. Then, the wordline is turned ON
If the transistor is present, it pulls the bitline LOW
If the transistor is not present, the bitline remanins HIGH
Programming the 32x8 ROM
93
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 1 0 1
0 0 0 0 1 1 0 0 0 1 0 1 1
0 0 0 1 0 1 0 1 1 0 0 0 0

1 1 1 0 1 0 0 0 1 0 0 0 0
1 1 1 1 0 0 1 0 1 0 1 1 0
1 1 1 1 1 1 1 1 0 0 0 0 1
0
1
2
29
30
31
D7 D6 D5 D4 D3 D2 D1 D0
A4
A3
A2
A1
A0
5-to-32

Decoder
Other Flavors of ROMs
Reprogrammable ROMs
EPROM (Erasable Programmable ROM)
Use UV (Ultra Violet) light for erasing
EEPROM (Electrically Erasable Programmable ROM)

Flash memory
Read and Writable
Non-volatile
Power off does not erase information stored

Modern ROMs are not really read-only
They can be reprogrammed as well

Flash memory has become extremely popular to store large
amounts of data in portable systems such as cameras and music
players

94

CHAPTER 5. Memory Element: Electrical Engineering Department PTSB

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CHAPTER 5. Memory Element: Electrical Engineering Department PTSB

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CHAPTER 5.

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