Sri Siddhartha Institute of Technology

Project Phase-3 seminar

on
FPGA IMPLEMENTATION OF DCTQ
PROCESSOR


BY
VISHALAKSHI G R
Reg.No.: 5WH08LDZ19

UNDER THE GUIDANCE
VINUTHA C.B ,M.tech
Lecturer,Dept. of E & C, SSIT, Tumkur
A picture is worth more than a thousand
words
Presentation Flow
1. Objective.
2. Introduction to Image Compression Technique using
DCTQ.
3. 2-dimensional Discrete cosine transform
4. Hardware Implementation
5. Results and Discussions
6. Advantages and Applications
7. Conclusion and Future work





Objectives
1. The objective of this project is to conduct a comparative study of
some commonly used transform-based visual feature extraction
techniques (variants of 2D DCT) and its both Matlab and FPGA
implementations.

2. The algorithm is optimized for speed and power.

3. The complete algorithm is pipelined and parallel processed for
video applications.

4. In addition, this project also experiments with quantization
techniques.


The discrete cosine transform (DCT) is a technique for
converting a signal into elementary frequency
components.
It is widely used in image compression
INTRODUCTION
INTRODUCTION
Need FOR COMPRESSION
1.JPEG, JPEG 2000 for still images.

2. MPEG 1, MPEG 2, MPEG 4, H.264, MPEG 7 for
motion pictures.

3.Multimedia hyper-media experts group (MHEG).

4.High Definition Television(HDTV)

5. H.261/H.263 for videophone and video conferencing.

Standards available for image/video sequences:
1.Matlab Implementation of DCTQ

2.Verilog Implementation of DCTQ

3.Test bench for DCTQ

4.Verification using standard test images like Lena,
Cameraman etc.


METHODOLOGY
DCT is an orthogonal transform consisting of a set of
vectors that are sampled cosine functions .

2D-DCT of a block of size 8 8 pixels of an image is
defined as

2-dimentional discrete cosine transform
The DCT can be expressed conveniently in a matrix form:

DCT=CXC
T



Hardware implementation
SYStem operation
SYStem operation
SYStem operation
results and discussions
1.Tool used : Matlab version 8.0
2.Window size chosen : 33.
3.Resolution of test images: 256256 pixels
4.Experiment is conducted for variety of test
images.

simulation results(dctq)
Simulation results (iqidctq)
First Column: (a) Original Image with resolution 256256;
Second Column: (b) Reconstructed Image by ( DCTQ and IQIDCT )
MATLAB;
Third Column: (c) Reconstructed Image by (DCTQ and IQIDCT)
Verilog HDL;

1. In order to meet the real-time requirements, DCT and
IDCT implementations use efficient and dedicated
hardware.
2. A linear, highly pipelined, parallel algorithm and
architecture have been proposed for 2D-DCT and
Quantization on FPGAs.
applications
Education
Industries
Medicine
Defense & training
Entertainment
Sports
Multimedia
desktop publishing
videophone
video conferencing
digital cameras
digital TV
digital cinema, and so on.

References
[1] R. C. Gonzalez and R. E. Woods, Digital Image Processing Reading, MA: Addison-
Wesley, 1992.

[2] ISO/IEC MPEG-2 Standards for generic coding of moving pictures: Part 2, Video, 1998.

[3] N.I. Cho, S.U. Lee, Fast Algorithm and Implementation of 2D-Discrete Cosine Transform,
IEEE Transactions on Circuits and Systems, Vol. CAS 38, pp. 297 - 305, Mar. 95.

[4] H. Park and V.K. Prasanna, Area efficient VLSI architectures for Huffman coding, IEEE
Transactions on circuits and systems, Vol. 40, No. 9, pp. 568-575, Sep.1993.

[5] H.C. Chang, L.G. Chen, Y.C. Chang, S.C. Huang, A VLSI Architecture Design of VLCEncoder
for High Data Rate Video/Image Coding, IEEE International symposium on circuits and systems,
Orlando, Florida, pp. iv398-401, May-June 1999.

[6] S. Ramachandran and S. Srinivasan, A fast, FPGA-based MPEG-2 video encoder with a novel
Automatic quality control scheme, Elsevier, Journal of Microprocessors and Microsystems, UK,
25, pp. 449-457, 2002.


References
[7] S. Ramachandran and S. Srinivasan, Design and Implementation of an EPLD-basedVariable
Length Coder for Real Time Image Compression Applications, IEEE International symposium on
circuits and systems (ISCAS), Geneva, Switzerland, May, 2000.

[8] N. Ahmed, T. Natarajan and K.R. Rao, Discrete Cosine Transform, IEEE Trans. Computers, Vol. C-
23, pp. 90-94, 1974.

[9] Jian Huang and Jooheung Lee Yimin Ge, An Array-based Scalable Architecture for DCT
Computations in Video Coding IEEE Int. Conference Neural Networks & Signal Processing,
Zhenjiang, China, June 8~10, 2008

[10] Jian Huang and Jooheung Lee, Unified architecture for video coding, in Proc. IEEE
Symposium on Low-Power and High-Speed Chips (Coolchips XI), April 2008.

[11] T.S. Chang, C.S. Kung, and C.W. Jen, A simple processor core design for DCT/IDCT, IEEE Trans
Circuits Syst. Video Technol., Vol. 10, No. 3, April 2000.

[12] D. Gong, Y. He, and Z. Cao, New cost-effective VLSI implementation of a 2-D discrete cosine
transform and its inverse, IEEE Trans. Circuits Syst. Video Technol., Vol. 14, No.4, April 2004.

[13] A.Shames, W. Pan, A. Chidanandan, and M.A. Bayoumi, A low power high performance
Distributed DCT architecture, in proc. IEEE Computer Society Annual Symposium on VLSI,
2002.