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STATEMENT
Pengertian
Loop statements digunakan untuk operasi yang
berulang-ulang
Terdiri dari statement : for loops atau while loops
Statement for akan mengeksekusi sampai nomor
tertentu secara berulang, (controlling number)
Statement while akan mengeksekusi perintah
terus selama kondisi disyaratkan masih benar.
Contoh statement
Contoh untuk mereset FIFO secara asinkron
for i in 7 downto 0 loop
fifo(i) <= (others => 0);
end loop;
Skip condition
Misalnya jika reset diaktifkan semua array fifo bernilai 0 kecuali
fifo (4) register.
reg_array : process (rst , clk)
begin
if rst = 1 then
for i in 7 downto 0 loop
if i = 4 then
next;
else
fifo(i) <= (others => 0);
end if;
end loop;
.
Alternative statement
Reg_array: process(rst,clk)
begin
if rst = 1 then
loop1: for i in deep downto 0 loop
exit loop1 when i > 20;
fifo(i) <= (others => 0);
end loop;
Array bit
if wr = 1 then
for i in 7 downto 0 loop
if en(i) = 1 then
fifo(i) <= data_in;
else
fifo(i) <= fifo(i);
end if;
end loop;
end if;
Mendisain FIFO
--------------------------------------------------------------------------------- Title
: fifo8x9
-- Design : fifo
-- Author :
-- Company :
---------------------------------------------------------------------------------- File
: d:\vhdl\my_design\fifo\fifo\src\fifo.vhd
-- Generated : Sun Oct 19 17:39:03 2014
-- From
: interface description file
-- By
: Itf2Vhdl ver. 1.22
--
--------------------------------------------------------------------------------- Description :
--------------------------------------------------------------------------------
entity fifo8x9 is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd : in STD_LOGIC;
wr : in STD_LOGIC;
rdinc : in STD_LOGIC;
wrinc : in STD_LOGIC;
rdptrclr : in STD_LOGIC;
wrptrclr : in STD_LOGIC;
);
end fifo8x9;
--}} End of automatically maintained section
begin
---- fifo register array :
reg_array: process (rst, clk)
begin
if rst = '1' then
for i in 7 downto 0 loop
fifo(i) <= (others => '0');
end loop;
elsif (clk'event and clk = '1') then
if wr = '1' then
for i in 7 downto 0 loop
if en(i) = '1' then
fifo(i) <= data_in;
else
fifo(i) <= fifo(i);
end if;
end loop;
end if;
end if;
end process;
begin
end if;
end if;
end process;
begin
end if;
end if;
end process;
begin
if rd = '1' then
else
end if;
end process;