Documente Academic
Documente Profesional
Documente Cultură
Lecture 1
Instructor Introduction
Course Introduction
Introduction to Verilog
Instructor
Dr. Vo Le Cuong
Email: vlcuong231@yahoo.com or
cuong.vole@hust.edu.vn
Mobile: 0938628986
Reseach Directions
Instructor
Dr. Vo Le Cuong
Reseach Directions (cont.)
2. Development of 3D camera (collaboration with KAIST,
Korea)
-Image sensor design: (1) Increasing SNR, (2) Reducing cross
talk.
-Image signal processing: (1) Depthmap extraction: accuracy
and real time processing, (2) High quality color: shapness, color
restoration.
3. Cars headlight detection (collaboration with KAIST,
Korea)
-Application for Intelligent transport system.
-Application for traffic observation at night.
4. High speed video camera (collaboration with
Ritsumeikan University, Korea)
3
Course Goals
Course Materials
Lectures
Textbook
Standards
Approximately:
Class Project
Forming teams
Project status report two times before the last report
Final demonstration & report at the last week of class
Course Tools
Read Chapter 3
10
Why Digital?
Chapter 1
Advantages
Advantage of digital devices
- Reproducibility of information
- Flexibility and functionality: easier to store, transmit
and manipulate information
- Economy: cheaper device and easier to design
Moores law
- Transistor geometry
- Chips double its density (number of transistor) in
every 18 months
- Devices become smaller, faster and cheaper
- Now a chip consists of hundreds of million gates
- And we can have a wireless-PDA-MP3-playercamera-GPS-cell-phone.
RTL Hardware Design
by Cuong Vo Le
Chapter 1
Chapter 1
info
A
/
D
Data
compression
Data
encryption
Error
correction
coding
Modulation
digital implementation
info
D
/
A
Data decompression
Data
decryption
Error
correction
de-coding
Demodulation
digital implementation
receiver
Chapter 1
A
/
D
set point
Controller
D
/
A
actu
ator
Plant
Sen
sor
output
digital
implementation
Chapter 1
Chapter 1
Chapter 1
What is an HDL?
Simulating/Validating HDL
Stimulus
Generation
(verilog)
file
Design
Under Test
(verilog)
Output
Monitoring
Self Checking
(verilog)
file
20
What is Synthesis?
module counter(clk,rst_n,cnt);
input clk,rst_n;
output [3:0] cnt;
rst_n
clk
21
cnt[3:0]
if (a) f = c & d;
else if (b) f = d;
else f = d & e;
d
e
b
a
22
single vector
Synthesis tool does the bulk of the tedious repetitive work vs
schematic capture
Portable Design
Synthesis tool are very good from the boolean correctness point of view
If you have a logic error in your final design there is a 99.999% chance
that error exists in your behavioral code
Errors caused in synthesis fall in the following categories
Timing
Bad Library definitions
Bad coding stylesloppyness
25
Structural
Register Transfer Level (RTL)
Behavioral
E.g., timing of
an inverter
Gate Level Abstraction
Hardware Implementations
Full
Custom
Manual
VLSI
SemiCustom
Standard
Cell
Gate
Array
Programmable
FPGA
PLD
29
Standard Cells
30
FPGAs
Programmable hardware
Use small memories as truth tables of functions
Decompose circuit into these blocks
Connect using programmable routing
SRAM bits control functionality
FPGA Tiles
P
P2
P4
P6
P8
P1
P3
OUT
P5
P7
I1 I2 I3
31
What is a Netlist?
A1
comb
n1
B
C
I1
n2
A2
endmodule
32
FSM Review
Examples of FSMs
Counter
Vending machine
Traffic light controller
Bus Controller
Control unit of serial protocol (like RS232, I2C or SPI)
33
Mealy/Moore FSMs
Mealy
Inputs
Next State
Logic
Output
Logic
Outputs
State Register
Current State
Next State
FF
34
FSMs
Moore
Mealy
36
Verilog Module
37
Verilog Module
A[1:0]
2
input [1:0] A ;
output [3:0] D ;
assign D =
(A == 2'b00) ? 4'b0001 :
(A == 2'b01) ? 4'b0010 :
(A == 2'b10) ? 4'b0100 :
(A == 2'b11) ? 4'b1000 ;
Decoder
2-to-4
4
D[3:0]
endmodule
38
Verilog Module
module name
port list
input [1:0] A ;
output [3:0] D ;
assign D =
port
sizes
(A == 2'b00) ? 4'b0001 :
(A == 2'b01) ? 4'b0010 :
(A == 2'b10) ? 4'b0100 :
(A == 2'b11) ? 4'b1000 ;
endmodule
End module statement
A[1:0]
2
Decoder
2-to-4
4
D[3:0]
module
contents:
dataflow
statement
39
Module Styles
40
Structural
Structural design
Structural Example
module majority (major, V1, V2, V3) ;
output major ;
input V1, V2, V3 ;
wire N1, N2, N3;
and A0 (N1, V1, V2),
A1 (N2, V2, V3),
A2 (N3, V3, V1);
or Or0 (major, N1, N2, N3);
endmodule
V1
V2
A0
V2
V3
A1
V3
V1
A2
N1
N2
Or0
major
N3
majority
42
RTL Example
module majority (major, V1, V2, V3) ;
output major ;
input V1, V2, V3 ;
assign major = V1 & V2
| V2 & V3
| V1 & V3;
endmodule
V1
V2
V3
majority
major
43
Behavioral Example
module majority (major, V1, V2, V3) ;
V1
V2
V3
majority
major
endmodule
44
Things to do
Read Chapter 3
45
Review Questions
46