Programmable Logic Devices

Programmable
Logic Devices
Introduction
An IC that contains large numbers of gates, flip-flops,
etc. that can be configured by the user to perform
different functions is called a Programmable Logic
Device (PLD).
The internal logic gates and/or connections of PLDs can
be changed/configured by a programming process.
One of the simplest programming technologies is to use
fuses. In the original state of the device, all the fuses are
intact.
Programming the device involves blowing those fuses
along the paths that must be removed in order to obtain
the particular configuration of the desired logic function.
Programmable Logic Organization

PLDs are typically built with an array of AND gates (AND-array)
and an array of OR gates (OR-array).
"Personalized" by making or breaking connections among the
gates
Inputs
Programmable Array Block Diagram for Sum of Products Form
ADVANTAGES
less board space, faster, lower power requirements (i.e., smaller power supplies),
less costly assembly processes, higher reliability (fewer ICs and circuit
connections means easier troubleshooting), and availability of design software.
Basic Programmable Logic

Organizations
Depending on which of the AND/OR logic
arrays is programmable, we have three
basic organizations
ORGANIZATION
AND ARRAY
OR ARRAY
PAL
PROG.
FIXED
PROM
FIXED
PROG.
PLA
PROG.
PROG.
ROM, PAL and PLA Configurations

Fixed
AND array
(decoder)
Inputs
Programmable
Connections
Programmable
OR array
Outputs
(a) Programmable read-only memory (PROM)
Inputs
Programmable
Connections
Programmable
AND array
Fixed
OR array
Outputs
Programmable
OR array
Outputs
(b) Programmable array logic (PAL) device
Inputs
Programmable
Connections
Programmable
AND array
Programmable
Connections
(c) Programmable logic array (PLA) device
Chapter 3 - Part 2
PLA Logic Implementation

Unprogrammed device
Alternative representation
Short-hand notation
so we don't have to
draw all the wires!
X at junction indicates
a connection
A B C D
AB
AB
CD
Notation for implementing
CD
F0 = A B + A B
F1 = C D + C D
Programmed device
AB+AB
CD+CD

Design Example
A B C
ABC
Multiple functions of A, B, C
A
B
F1 = A B C
C
A
F2 = A + B + C
F3 = A B C
ABC
F4 = A + B + C
ABC
F5 = A B C
ABC
ABC
F6 = A B C
ABC
ABC
ABC
F1 F2 F3 F4 F5
F6
PALs and PLAs

What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept implemented by Monolithic Memories
AND array is programmable, OR array is fixed at fabrication
A given column of the OR array

has access to only a subset of
the possible product terms
PLA concept Both AND and OR arrays are programmable
PALs and PLAs

Of the two organizations the PLA is the
most flexible
One PLA can implement a huge range of logic
functions
BUT many pins; large package, higher cost
PALs are more restricted / you trade

number of OR terms vs number of outputs
Many device variations needed
Each device is cheaper than a PLA
PAL Logic Implementation

Design Example: BCD to Gray Code Converter
Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
AB
00
CD
A
01
11
10
00
01
AB
00
CD
A
01
11
10
00
01
11
10
D
11
C
10
B
K-map for W
AB
00
CD
Minimized Functions:
B
K-map for X
A
01
11
10
00
01
AB
00
CD
A
01
11
10
00
01
11
10
D
11
W=A+BD+BC
X=BC
Y=B+C
Z=ABCD+BCD+AD+BCD
K-maps
C
10
B
K-map for Y
B
K-map for Z
PAL Logic Implementation

Programmed PAL:
A B
C D
A
BD
BC
Minimized Functions:
W=A+BD+BC
X=BC
Y=B+C
Z=ABCD+BCD+AD+BCD
BC
0
0
0
B
C
0
0
ABCD
BCD
AD
BCD
4 product terms per each OR gate

W

Another Example: Magnitude Comparator
AB
00
CD
A
01
11
10
AB
00
CD
ABCD
01
11
10
00
00
01
01
11
11
10
ABCD
ABCD
D
ABCD
C
10
AC
AC
K-map for EQ
K-map for NE
BD
BD
AB
00
CD
A
01
11
10
AB
00
CD
A
01
11
10
ABD
00
00
BCD
01
01
ABC
11
11
10
10
D
C
BCD
B
K-map for LT
B
K-map for GT
EQ NE LT
GT

Programmable Logic Devices

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Programmable Logic Devices

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Programmable

Programmable Logic Organization

Programmable Array Block Diagram for Sum of Products Form

Basic Programmable Logic

ROM, PAL and PLA Configurations

(a) Programmable read-only memory (PROM)

(b) Programmable array logic (PAL) device

(c) Programmable logic array (PLA) device

PLA Logic Implementation

Notation for implementing

PLA Logic Implementation

PALs and PLAs

A given column of the OR array

PLA concept Both AND and OR arrays are programmable

PALs and PLAs

PALs are more restricted / you trade

PAL Logic Implementation

PAL Logic Implementation

4 product terms per each OR gate

PLA Logic Implementation

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