EE603

COURSE
: EE603 CMOS INTEGRATED CIRCUIT DESIGN
INSTRUCTIONAL DURATION : 15 WEEKS
CREDIT(S)
: 2
PRE REQUISITE(S)
: NONE

SYNOPSIS
CMOS INTEGRATED CIRCUIT DESIGN course exposes the students to the basic
principles of CMOS integrated circuit design, with comprehensive overview of the
MOSFET transistor theory. Furthermore, the students will be equipped with the
knowledge to design nucleus of digital design, the inverter, and designing simple to
complex digital CMOS gates. Finally, the students will experience developing the physical
layout of an integrated circuit using CAD tools complying with specific
design rules.

EE603 CMOS INTEGRATED CIRCUIT DESIGN

Lecturer : En. Sivadev Nadarajah

Phone #:
019-5767442
Email ID: sivadev@yahoo.com

NOR HALIZA ABDUL HAMID JKE/PUO

CMOS INTEGRATED CIRCUIT DESIGN

COURSE LEARNING OUTCOMES (CLO)

3. construct the basic logic gates using static and dynamic CMOS
techniques.(C3)
4. draw the layout design of a CMOS circuit using layout design software
based on specific CMOS layout design rules. (P3)
5. perform communication skill through oral presentation on a given topic. (A2)

NOR HALIZA ABDUL

2. explain clearly the operation theory and transistor characteristics of

MOS and CMOS transistors. (C2)

HAMID JKE/PUO

1. explain correctly the basic principles of integrated circuit design,

design metrics, design methodology and design hierarchy of CMOS
IC design. (C2)

EE603 CMOS INTEGRATED CIRCUIT DESIGN

Upon completion of this course, students should be able to:

(02 : 00)

3.0 THE DEVICE

Comprehensive overview of the operation of diode and MOS transistor. Issues in
Sub-Micron MOS Transistor design.

(06 : 08)

4.0 THE WIRE

Impact of Interconnect Parasitic: capacitances, resistance and inductance on integrated
circuit design.

(04 : 00)

5.0 THE CMOS INVERTER

Voltage Transfer Characteristic of an inverter. Design for Performance. Inverter Sizing.
Power Dissipation. Impact of Technology Scaling.

(06 : 10)

6.0 DESIGNING COMBINATIONAL LOGIC CIRCUITS

Static CMOS Circuit. Complementary CMOS Logic Style. Cell Design. Rationed Logic.
Dynamic Logic

(08 : 12)

7.0 DESIGN METHODOLOGY

Design hierarchy and methodology: standard IC, specific custom IC, Full-custom IC,
semi-custom IC, gate-array, standard cell, and programmable logic device (PLD).

(02 : 00)

JKE/PUO

2.0 MANUFACTURING PROCESS

Manufacturing process revisited. The concept of design rules. Issues related to designing
the layout of an integrated circuit.

NOR HALIZA ABDUL HAMID

(30 LECTURE : 30 PRACTICAL)

RTA
1.0 INTRODUCTION TO INTEGRATED CIRCUIT
(02 : 00)
Evolution in integrated circuit. Fundamental of design metrics that govern digital design.
Performance evaluation of a digital circuit. Issues in digital design.

EE603 CMOS INTEGRATED CIRCUIT DESIGN

SUMMARY

ASSESSMENT

NOR HALIZA ABDUL HAMID

ii. Final Examination (FE) 50%

Final examination is carried out at the end of the semester.

JKE/PUO

i. Coursework (CA) - 50%

Coursework is continuous assessment that measures knowledge,
technical skills and soft skills.

EE603 CMOS INTEGRATED CIRCUIT DESIGN

The course assessment is carried out in two sections:

JKE/PUO

NOR HALIZA ABDUL HAMID

EE603 CMOS INTEGRATED CIRCUIT DESIGN

Rabaey, J. M, Anantha Chandrakasan, Borivoje Nikolic. (2003). Digital Integrated

Circuit, Prentice Hall, Inc.
Uyemura, J. P. (2006). Chip Design for Submicron VLSI . Nelson, Thompson of
Canada Ltd.
V.S.Bagad (2009). VLSI Design. Technical Publications.
Weste, N, Eshraghian.K. (2000). Principles of CMOS VLSI Design. Addison-Wesley

NOR HALIZA ABDUL HAMID JKE/PUO

Adel S. Sedra and Kenneth Carless. Smith(2003). Microelectronic Circuits. Oxford

University Press

EE603 CMOS INTEGRATED CIRCUIT DESIGN

REFERENCES