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Based 2 Bit
Comparator
ABSTRACT
Comparison is most basic arithmetic operation that
determines if one number is greater than, equal to, or less
than the other number.
Comparators
WHAT IS A COMPARATOR?
Magnitude comparator is a
combinational circuit that compares
two numbers, A and B, and
determines their relative
magnitudes.
Truth Table
INPUT
A1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
OUTPUT
B0
0
1
B1
0
0
0
0
A0
0
0
Digital
Circuits
Static Circuits
Classical
CMOS
Transmissio
n Gates
Dynamic Circuits
Pseudo
NMOS
Pass
Transisto
r
Domino Logic
Design
produces
Large
Power
dissipation in comparison to remaining
three logic styles.
Design requires large number of
transistors because for every input both
(NMOS & PMOS) are used
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Design requires
transistors
large
number
of
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PARAMETER
CONVENTIONAL
DYNAMIC
Transistor used
2N
N+4
Speed
less
more
Area used
more
less
Power dissipation
more
less
Delay
more
less
Noise margin
low
high
Efficiently
less
more
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During the precharge phase (when CK = 0), the output node of the dynamic CMOS
stage is precharged to a high logic level, and the output of the CMOS inverter becomes
low. When the clock signal rises at the beginning of the evaluation phase, there are two
possibilities: The output node of the dynamic CMOS stage is either discharged to a low
level through the nMOS circuitry (1 to 0 transition), or it remains high.
Consequently, the inverter output voltage can also make at most one transition during
the evaluation phase, from 0 to 1. Regardless of the input voltages applied to the
dynamic CMOS stage, it is not possible for the buffer output to make a 1 to 0 transition
during the evaluation phase.
The problem in cascading conventional dynamic CMOS stages occurs when one or
more inputs of a stage make a 1 to 0 transition during the evaluation phase .On the
other hand, if we build a system by cascading domino CMOS logic gates ,all input
transistors in subsequent logic blocks will be turned off during the precharge phase,
since all buffer outputs are equal to 0. During the evaluation phase, each buffer output
can make at most one transition (from 0 to 1), and thus each input of all subsequent
logic stages can also make at most one (0 to 1) transition.
In a cascade structure consisting of several such stages, the evaluation of each stage
ripples the next stage evaluation, similar to a chain of dominos falling one after the other.
The structure is hence called domino CMOS logic.
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Advantages
Speed advantages
Disadvantages
Non-inverting nature may require logic duplication
Strict timing constraints
Charge sharing, noise susceptibility
High clock routing overhead
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CONCLUSION
Less number of transistors are used in
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References
Circuits, Power and Computing Technologies (ICCPCT), 2013
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Thanks
For Your
Patient
Listening
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