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Design Specification
Timing
Specification
Design Specification
Design Specification
Algorithm
No of I/O with bits info
Functionally
No
No of bits in internal operations
Correct?
No of Clock signals
Yes
Max Clock freq used
Planning Placement Routing
Area of Chip
Power Dissipation in Chip
No(if first iterations failed Design
No(if first iterations failed
Routed
Yes
Timing Simulation and
Analysis
Functional Simulation/ Logical Verification
Timing
Specification
Design Specification
Design Entry
Timing
Specification
Schematic
Verilog HDL
VHDL
Design Specification
Functional Simulation
Timing
Specification
Design Specification
PPR
Timing
Specification
Partitioning
Floor planning
Placement
Routing
Design Specification
Timing Simulation
Timing
Specification
Net Delays
Gate Delays
Design Specification
Fusing and Fabrication
into chip
Timing
Specification
ASICs
FPGAs
CPLDs
Gate Arrays
SOGs