Introduction to

CMOS VLSI
Design

CMOS Transistor Theory

Outline

Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models

CMOS VLSI Design

MOS devices
Slide 2

Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
Also explore what a degraded level really means

CMOS VLSI Design

MOS devices
Slide 3

MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
Vg < 0

+
-

polysilicon gate
silicon dioxide insulator
p-type body

(a)

0 < Vg < Vt

+
-

depletion region

(b)

V g > Vt
+
-

inversion region
depletion region

(c)

CMOS VLSI Design

MOS devices
Slide 4

Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs
Vgd = Vg Vd
Vds = Vd Vs = Vgs - Vgd

Vg
+
Vgd
-

+
Vgs
Vs

Vds

Vd

Source and drain are symmetric diffusion terminals

By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
CMOS VLSI Design

MOS devices
Slide 5

nMOS Cutoff
No channel
Ids = 0
Vgs = 0

+
-

+
-

Vgd

n+

n+
p-type body
b

CMOS VLSI Design

MOS devices
Slide 6

nMOS Linear
Channel forms
Current flows from d to s
V
e- from s to d
Ids increases with Vds
Similar to linear resistor

gs

> Vt

+
-

+
-

Vgd = Vgs

n+

Vds = 0

n+
p-type body
b

Vgs > Vt

+
-

+
d

n+

n+

Vgs > Vgd > Vt

Ids
0 < Vds < Vgs-Vt

p-type body
b

CMOS VLSI Design

MOS devices
Slide 7

nMOS Saturation

Channel pinches off

Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt

+
-

+
-

Vgd < Vt

d Ids

n+

n+

Vds > Vgs-Vt

p-type body
b

CMOS VLSI Design

MOS devices
Slide 8

I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?

CMOS VLSI Design

MOS devices
Slide 9

Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel =

gate
Vg

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.9)

+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body

p-type body

CMOS VLSI Design

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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
C=
gate
Vg

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.9)

+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body

p-type body

CMOS VLSI Design

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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V=
gate
Vg

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.9)

+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body

p-type body

CMOS VLSI Design

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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
gate
Vg

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.9)

+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body

p-type body

CMOS VLSI Design

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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v=

CMOS VLSI Design

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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E=

CMOS VLSI Design

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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=

CMOS VLSI Design

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Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral E-field
between source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=L/v

CMOS VLSI Design

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nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

I ds

CMOS VLSI Design

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nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

Qchannel
I ds
t

CMOS VLSI Design

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nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

Qchannel
I ds
t
W
Cox
L

V V Vds V
gs t
ds
2

V
Vgs Vt ds Vds
2
CMOS VLSI Design

W
= Cox
L
MOSSlide
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nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

I ds

CMOS VLSI Design

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nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

I ds Vgs Vt

Vdsat
Vdsat

CMOS VLSI Design

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nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

I ds Vgs Vt

Vgs Vt
2

Vdsat
Vdsat

CMOS VLSI Design

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nMOS I-V Summary

Shockley 1st order transistor models

Vgs Vt

Vds

I ds Vgs Vt
Vds Vds Vdsat

Vgs Vt
Vds Vdsat

2
CMOS VLSI Design

cutoff
linear
saturation

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Example
Example: a 0.6 m process from AMI semiconductor
tox = 100
= 350 cm2/V*s
2.5
V =5
Vt = 0.7 V
2
Plot Ids vs. Vds
1.5
V =4
Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2

Ids (mA)

gs

gs

1
0.5
0

3.9 8.85 1014

W
Cox 350
L
100 108

Vgs = 3

W
W

120
A /V 2

L
L

CMOS VLSI Design

Vgs = 2
Vgs = 1

Vds

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pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume n / p = 2

CMOS VLSI Design

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Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS VLSI Design

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Gate Capacitance
Approximate channel as connected to source
Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/m

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.90)

p-type body
CMOS VLSI Design

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Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process

CMOS VLSI Design

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Pass Transistors
We have assumed source is grounded
What if source > 0?
VDD
e.g. pass transistor passing VDD
VDD

CMOS VLSI Design

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Pass Transistors
We have assumed source is grounded
What if source > 0?
VDD
e.g. pass transistor passing VDD
VDD
Vg = VDD
If Vs > VDD-Vt, Vgs < Vt
Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded 1
Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
CMOS VLSI Design

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Pass Transistor Ckts

VDD

VDD

VDD

VDD

VDD

VDD

VDD
VDD
VSS

CMOS VLSI Design

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Pass Transistor Ckts

VDD

VDD

VDD
Vs = VDD-Vtn

Vs = |Vtp|

VDD

VDD

VDD

VDD-Vtn VDD-Vtn
VDD

VDD-Vtn

VDD-Vtn
VDD

VSS

CMOS VLSI Design

VDD-2Vtn

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Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay

CMOS VLSI Design

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RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
d

d
k
s

s
kC

R/k
g

kC

kC
s

d
k
s

kC
2R/k

kC
kC
d

CMOS VLSI Design

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RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent
CMOS VLSI Design

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Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2 Y

CMOS VLSI Design

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Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter
2C
R

2 Y

2C

2C
Y

CMOS VLSI Design

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Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter
2C
R

2 Y

2C

2C

2C

2C

Y
R

R
C

C
C

CMOS VLSI Design

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Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter
2C
R

2 Y

2C

2C

2C

2C

Y
R

R
C

C
C

d = 6RC
CMOS VLSI Design

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