DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 1

VHDL
A FIRST LOOK

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 2

Why HDLs?
In software everything is sequential
Sequence of statements is significant, since they are
executed in that order
In hardware events are concurrent, so a software
language cannot be used for describing and simulating
hardware.

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 3

e.g.
C = (not (X) and Y) or (not (X))
1 -> 0
X

A 0 -> 1
C

Case 1
A = not X
B = A and Y
C = A or B
Result:
C=1
2002

Case 2
B = A and Y
C = A or B
A = not X
Result:
C=0

Centre for Development of Advanced Computing

Case 3
C = A or B
A = not X
B = A and Y
Result:
C=0

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 4

Features of HDLs
Concurrent Descriptions
Synchronizing mechanisms between concurrent
flows
Event Scheduling
Special object types and data types
Hierarchy

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 5

HDL Implementation Design

Cycle
DESIGN ENTRY
Schematic , VHDL, Verilog,
etc.
Functional Simulation

IP cores
Static Timing Analysis
Gate level simulation

SYNTHESIS
Test insertion

LIBRARIES
Static Timing Analysis

Post layout simulation

2002

Implementation
MAP, PLACE,
ROUTE

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 6

Advantages of using Hardware Description Languages

Designs can be described at various levels of abstractions
Top-Down Approach and hierarchical designs for large projects
Functional Simulation Early in the Design Flow
Automatic Conversion of HDL Code to Gates
With user level control. Consistent quality. Fast.

Early Testing of Various Design Implementations

Due to fast synthesis, there is a scope for trying different implementations .

Design Reuse
Technology independence, standardization, portability, ease of maintenance.

All this results in low risk, high convergence, fast time to market, more
money.
2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 7

A Brief History Of VHDL

VHDL stands for Very high speed integrated circuit Hardware
Description Language

Funded by the US Department of Defense in the 70's and 80's

Originally meant for design standardisation, documentation,

simulation and ease of maintenance.

Established as IEEE standard IEEE 1076 in 1987. An updated

standard, IEEE 1164 was adopted in 1993. In 1996 IEEE 1076.3
became a VHDL synthesis standard.

Today VHDL is widely used across the industry for design

description, simulation and synthesis.

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 8

About VHDL
VHDL is not case sensitive
VHDL is a free form language. You can write the
whole program on a single line.
-- This is a VHDL comment
entity my_exor is -- one more comment
Port(
...);
end my_exor;
2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 9

my EXOR gate
-- This is my first VHDL program
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
end my_exor;

2002

Centre for Development of Advanced Computing

entity
entitydeclaration
declaration--describes
describesthe
the
boundaries
boundariesof
ofthe
theobject.
object.
ItItdefines
definesthe
thenames
namesof
ofthe
theports,
ports,their
their
mode
modeand
andtheir
theirtype.
type.

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 10

my EXOR gate
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
end my_exor;

2002

Centre for Development of Advanced Computing

entity
entity- -defines
definesthe
the
interface.
interface.

Mode
Modeof
ofthe
theport
port::
Direction
Directionof
offlow.
flow.
ItItcan
canbe
be
in,
in,out
outor
orinout
inout

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 11

my EXOR gate
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
Mode
Modeof
ofthe
theport
port: :
end my_exor;
ItItcan
canbe
be
in,
out
in, outor
orinout
inout

2002

Centre for Development of Advanced Computing

entity
entity- -defines
definesthe
the
interface.
interface.

std_logic
std_logicisisthe
thetype
typeof
ofthe
the
port.
port.
Standard
Standardlogic
logicis
isdefined
defined
by
bythe
thestandard
standard
IEEE
IEEE1164.
1164.
ItItis
isdefined
definedin
inthe
theIEEE
IEEE
library.
library.
Any
Anynode
nodeof
oftype
typestd_logic
std_logic
can
cantake
take99different
differentvalues.
values.
0
0, ,1
1, ,H
H, ,L
L, ,Z
Z, ,
U
U, ,X
X, ,W
W, ,-
-

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 12

my EXOR gate
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
end my_exor;

2002

Centre for Development of Advanced Computing

Library
Library::Collection
Collectionof
ofdesign
design
elements,
elements,type
typedeclarations,
declarations,sub
sub
programs,
programs,etc.
etc.

DIPLOMA IN VLSI DESIGN

my EXOR gate
library IEEE;
use IEEE.std_logic_1164.all;

VHDL - A FIRST LOOK 13

Library
Library: :Collection
Collectionof
ofdesign
design
elements,
type
declarations,sub
elements, type declarations,sub
programs,
programs,etc.
etc.

entity
entity my_exor is
entity- -defines
definesthe
the
interface.
port (ip1
: in std_logic;
interface.
ip2
: in std_logic;
std_logic
op1
: out std_logic
std_logicisisthe
thetype
typeof
ofthe
theport
port
ItItisisdefined
);
definedin
inthe
theIEEE
IEEElibrary.
library.
Mode
of
the
port
:
Mode
of
the
port
:
Any
end my_exor;
Anynode
nodeof
oftype
typestd_logic
std_logiccan
cantake
take
ItItcan
be
can be
99different
values.
different values.
in,
in,out
outor
orinout
inout
0
0, ,1
1, ,H
H, ,L
L, ,Z
Z, ,U
U, ,X
X, ,W
W, ,-
-
architecture my_exor_beh of my_exor is
begin
op1 <= (ip1 and (not ip2)) or
The
Thearchitecture
architecturedescribes
describesthe
the
(ip2 and (not ip1));
behaviour
behaviour(function),
(function),
end my_exor_beh;

interconnections
interconnectionsand
andthe
the
relationship
relationshipbetween
betweendifferent
different
inputs
inputsand
andoutputs
outputsof
ofthe
theentity.
entity.

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

my EXOR gate
library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1
: in std_logic;
ip2
: in std_logic;
op1
: out std_logic
);
Mode
end my_exor;
Modeof
ofthe
theport
port: :
ItItcan
canbe
be
in,
out
in, outor
orinout
inout
architecture my_exor_beh of my_exor is
begin
op1 <= (ip1 and (not ip2)) or
(ip2 and (not ip1));
end my_exor_beh;
configuration my_exor_C of my_exor is
for my_exor_beh
end for;
end my_exor_C;
2002

Centre for Development of Advanced Computing

VHDL - A FIRST LOOK 14

Library
Library: :Collection
Collectionof
ofdesign
design
elements,
type
declarations,
elements, type declarations,
sub
subprograms,
programs,etc.
etc.
entity
entity- -defines
definesthe
the
interface.
interface.
std_logic
std_logicisisthe
thetype
typeof
ofthe
theport
port
ItItisisdefined
definedin
inthe
theIEEE
IEEElibrary.
library.
Any
node
of
type
std_logic
Any node of type std_logiccan
cantake
take
99different
value.
different value.
0
0, ,1
1, ,H
H, ,L
L, ,Z
Z, ,U
U, ,X
X, ,W
W, ,-
-
The
Thearchitecture
architecturedescribes
describesthe
the
behaviour(function),
behaviour(function),interconnections
interconnections
and
andthe
therelationship
relationshipbetween
betweendifferent
different
inputsand
outputs.
inputsand outputs.

The
Theconfiguration
configurationisisoptional.
optional.
ItItdefines
definesthe
theentity
entityarchitecture
architecture
bindings.
bindings.
More
Moreabout
aboutconfigurations
configurationslater.
later.

DIPLOMA IN VLSI DESIGN

Internal connections are made using signals.

Signals are defined inside the architecture.

architecture
architecture my_exor_beh
my_exor_beh of
of my_exor
my_exor is
is
signal
signal temp1
temp1 :: std_logic;
std_logic;
signal
signal temp2
temp2 :: std_logic;
std_logic;
begin
begin
......
......
end
end my_exor_beh;
my_exor_beh;

2002

Centre for Development of Advanced Computing

VHDL - A FIRST LOOK 15

DIPLOMA IN VLSI DESIGN

my EXOR with internal signals

library
library IEEE;
IEEE;
use
use IEEE.std_logic_1164.all;
IEEE.std_logic_1164.all;
entity
entity my_exor
my_exor is
is
port
(ip1
:
in
port (ip1
: in std_logic;
std_logic;
ip2
:
in
std_logic;
ip2
: in std_logic;
op1
op1 :: out
out std_logic
std_logic
);
);
end
my_exor;
end my_exor;
architecture
architecture exor_w_sig
exor_w_sig of
of my_exor
my_exor is
is
signal
signal temp1,
temp1, temp2
temp2 :: std_logic;
std_logic;
begin
begin
temp1
temp1 <=
<= ip1
ip1 and
and (not
(not ip2);
ip2);
temp2
<=
ip2
and
(not
ip1);
temp2 <= ip2 and (not ip1);
op1
op1 <=
<= temp1
temp1 or
or temp2;
temp2;
end
end exor_w_sig;
exor_w_sig;
configuration
configuration my_exor_C
my_exor_C of
of my_exor
my_exor is
is
for
exor_w_sig
for exor_w_sig
end
end for;
for;
end
end my_exor_C;
my_exor_C;
2002

Centre for Development of Advanced Computing

VHDL - A FIRST LOOK 16

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 17

Test Benches.
To test a circuit we will design another circuit (test bench) which
will generate the signals required to test our circuit. Interestingly
this new circuit is also described in VHDL.

my_EXOR_TST

my_EXOR

Test
Process

ip1
op1
ip2

Test Benches should be as simple as possible

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 18

entity
entity my_exor_tst
my_exor_tst is
is
end
my_exor_tst;
end my_exor_tst;
my_EXOR_TST
ip1_s

Test

my_EXOR

process

op1_s
ip2_s

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 19

entity
entity my_exor_tst
my_exor_tst is
is
end
my_exor_tst;
end my_exor_tst;
my_EXOR_TST

architecture
architecture my_exor_tst_A
my_exor_tst_A of
of my_exor_tst
my_exor_tst is
is
component
component my_exor
my_exor
ip1_s
port
(ip1
port (ip1 :: in
in std_logic;
std_logic;
ip2
Test
ip2 :: in
in std_logic;
std_logic;
my_EXOR
op1
op1 :: out
out std_logic);
std_logic);
process
end
op1_s
end component;
component;
ip2_s
signal
signal ip1_s,
ip1_s, ip2_s,
ip2_s, op1_s
op1_s :: std_logic;
std_logic;
begin
begin
U1:
U1: my_exor
my_exor
port
port map(
map( ip1
ip1 =>
=> ip1_s,
ip1_s,
ip2
ip2 =>
=> ip2_s,
ip2_s,
op1
=>
op1_s
op1 => op1_s );
);
........
........
COMPONENT
end
my_exor_tst_A;
end my_exor_tst_A;

INSTANTIATION

2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

entity
entity my_exor_tst
my_exor_tst is
is
end
my_exor_tst;
end my_exor_tst;

VHDL - A FIRST LOOK 20

my_EXOR_TST

architecture
ip1_s
architecture my_exor_tst_A
my_exor_tst_A of
of my_exor_tst
my_exor_tst is
is
component
Test
component my_exor
my_exor
my_EXOR
port
port (ip1
(ip1 :: in
in std_logic;
std_logic;
process
ip2
op1_s
ip2 :: in
in std_logic;
std_logic;
ip2_s
op1
op1 :: out
out std_logic);
std_logic);
end
end component;
component;
signal
signal ip1_s,
ip1_s, ip2_s,
ip2_s, op1_s
op1_s :: std_logic;
std_logic;
begin
begin
U1:
U1: my_exor
my_exor
CONFIGURATION
port
port map(
map( ip1
ip1 =>
=> ip1_s,
ip1_s,
ip2
ip2 =>
=> ip2_s,
ip2_s,
Library WORK
op1
=>
op1_s
);
op1 => op1_s );
........
........
end
end my_exor_tst_A;
my_exor_tst_A;
my_EXOR
configuration
my_exor_tst_C
of
my_exor_tst
is
configuration my_exor_tst_C of my_exor_tst is
for
for my_exor_tst_A
my_exor_tst_A
my_EXOR_beh
for
for U1
U1 :: my_EXOR
my_EXOR
use
use entity
entity work.my_EXOR(my_EXOR_beh);
work.my_EXOR(my_EXOR_beh);
end
for;
end for;
exor_w_sig
end
end for;
for;
end
end my_exor_tst_C;
my_exor_tst_C;
2002

Centre for Development of Advanced Computing

DIPLOMA IN VLSI DESIGN

architecture my_exor_tst_A of my_exor_tst is

......
begin
U1_my_EXOR : my_exor
port map( ip1 => ip1_s,
ip2 => ip2_s,
op1 => op1_s );
test_P : process
begin
ip1 <= 0;
ip2 <= 0;
wait for 10 ns;
ip1 <= 0;
ip2 <= 1;
wait for 10 ns;
ip1 <= 1;
ip2 <= 0;
wait for 10 ns;
ip1 <= 1;
ip2 <= 1;
wait for 10 ns;
end process;
end my_exor_tst_A;
2002

Centre for Development of Advanced Computing

VHDL - A FIRST LOOK 21

TEST PROCESS

DIPLOMA IN VLSI DESIGN

SUMMARY
Introduction to:
VHDL flow
Comments
Library declaration
Entity declaration (ports, modes, std_logic type)
Architecture
Signal declarations
Signal assignments
Component declaration and instantiation
Configuration statement
Test benches
Process statements
2002

Centre for Development of Advanced Computing

VHDL - A FIRST LOOK 22

DIPLOMA IN VLSI DESIGN

VHDL - A FIRST LOOK 23

THANK YOU

2002

Centre for Development of Advanced Computing