Sunteți pe pagina 1din 21

Under the guidance of

S.R.P Sinha
Associate Professor
(ECE Department)

Seminar Topic by
Daya Nand Gupta
M.Tech Micro-electronics
III Sem

The number of transistors in a dense integrated circuit doubles


approximately every 18 months.

(a) n-channel MOSFET


(b) Symbol of MOSFET
(c) Drain characteristics of n-channel MOS

When channel length decreases,


roll-off in the value of Vt
Tunneling through Gate oxide (off
state current)
Wastage area increases as density
increases

By moving to DG MOSFETs
Better control of channel from the gates
Reduced short-channel effects
Better Ion /Ioff
Improved (low) sub-threshold slope
(60mV/decade)

Fig.: DGT is comprised of a conducting channel (usually


un-doped), surrounded by gate electrodes on either side.

GENERAL DGT OPERATIONS


The voltage applied on the gate terminals controls the
electric field, determining the amount of current flow
through the channel. The most common mode of operation
is to switch both gates simultaneously.
Another mode is to switch only one gate and apply a bias to
the second gate (this is called ground plane (GP) or
back-gate (BG))

Fig: DGT operations

Different structures
Symmetrical and Asymmetrical

Fig. Symmetric and Asymmetric structure

Fig: Symmetrical DGFET (Work Function)

Fig. Asymmetrical DGFET (Work Function)

DGT Design Objectives

Reduction of short channel effects (SCEs)


-Decreased VT due to reduced channel
depletion charge
Maintaining good electrical characteristics
-High Ion/Ioff ratio
-Sharp I-V slope
-Keeping fabrication process simple

It is an effect whereby a MOSFET in which the channel length is


the same order of magnitude as the depletion layer widths of source
& drain junctions, behaves differently from the other MOSFETs.

As the channel length L is reduced to increase both the operation


speed and the number of components per chip, the so called SCE
occurs

Fig- Short channel effect in MOSFETS

Drain-induced barrier lowering or DIBL is


a short-channel effect in MOSFETs referring
originally to a reduction of threshold voltage of
the transistor at higher drain voltages.
Thus increased in Ioff

Fig-DIBL in MOSFETS

Ioff is defined as the drain current at Vgs = 0 V and


Vds = Vdd. Ideally, Ioff = 0
By placing a second gate on the opposite side of
the device, the gate capacitance of the channel is
doubled and the channel potential is better
controlled by the gate electrode, thus limiting Ioff.

Reduced channel and gate leakage


Short channel effects are seen in standard silicon
MOS devices
DGFET offers greater control of channel because of
double gate
Gate leakage current is prevented by a thick gate
oxide

Silicon MOS Transistor


Increased body doping used to control VT for short
channel
Small number of dopant atoms for very short channel
Lowest VT achievable is 0.5 V
Double Gate FET
Increased body doping
Asymmetric gate work functions (n+ /p+ gates)
VT of .1 V achievable through work function
engineering

Increase Carrier Mobility


Silicon MOS Transistor
Carrier scattering from increased
body doping
Transverse electric fields from the
source and
drain reduce
mobility
Double Gate FET
Lightly doped channel in a DGFET
results in a
negligible
depletion charge
Asymmetrical gate experiences
some transverse electric fields

Reduced Power Consumption


Double gate coupling allows for higher
drive currents at lower supply voltage and
threshold voltage
Energy is quadratic function of supply
Reduced channel and gate leakage currents
in off state translate to huge power savings
Separate control of each gate allows
dynamic control of VT

Reduction of off current Ioff , higher Ion current


Un-doped channel eliminates intrinsic parameter
fluctuations and minimizes impurity scattering.
Double gate allows for higher current drive
capability
Better control of short channel effects
Lower sub-threshold current
Lower gate leakage

Scaling

trend in CMOS approaching physical


limits prompts the need for alternative
device structures, such as DGT.
DGT is more robust to SCE, such as I of.
Major design challenge consists of achieving
good VT control, while keeping low R series.
Several structures have been proposed:
planar, vertical, and DG-FET
DGFET structure is so far the most promising.
Still major challenges remain ahead, specially
issues related to fabrication.

S-ar putea să vă placă și