Memory

Tri-State Buffer
Bus
Register Files
Memory
Scratch Pad Register
RAM Operation
Non-Volatile Memory (ROM)
PROM
EPROM
EEPROM

Tri-State Buffer
In digital electronics three-state, tri-state, or 3state logic allows an output port to assume a high
impedance state in addition to the 0 and 1 logic
level, effectively removing the output from the
circuit.

In active high control, if C=1, Y=X and

In active low control, if C=0, then
C=0, Y is isolated from X.
Y=X and when C=1, Y is isolated
from X.

Tri-State Buffer (TSB) - Application

Multiplexer
a) Using Basic Gates

b) Using TSB

X1
s
X0

Bus
Set of n signal lines (conducting wires) used together to
carry signal corresponding to address or control or data or
program (code) is known as BUS.

Fig (1)General diagram to show DATA, Address and Control Bus

Address
Bus (9)

Data
Memory
(512B)
Data
Bus (8)

Program
Memory
(8KW)

Address
Bus (13)

Program Memory
Bus (14)

Fig (2) PIC 16F877A - Program and Data Memory to show DATA, Address and Program Memory Bus

Register Files
A set of registers arranged in an orderly manner is
called a register file.
Types:
a) Serial Data is loaded one behind the other and
read in the similar manner

a) Parallel The register to which the data to be

transferred is directly accessed.

First In First Out (FIFO) Register file

Input

Reg Conte
Add nt
.
befor
e first
clock

Conte
nt
after
first
clock

I/P

Byte 1

A0
A1
A2
A3
O/P

Byte 0

Byte 0

FIFO

Output

Conten
t after
second
clock

Conten
t after
third
clock

Conten
t after
fourth
clock

Conten
t after
fifth
clock

Byte 2

Byte 3

Byte 4

Byte 5

Byte 1

Byte 2

Byte 3

Byte 4

Byte 0

Byte 1

Byte 2

Byte 3

Byte 0

Byte 1

Byte 2

Byte 0

Byte 1
Byte 0

Last In First Out (LIFO) Register file

Input /
Output

LIFO

Memory Parallel Register File

A parallel register file is more widely known as a
memory.
Classified based on 1. Hardware.
2. Size.
3. Function.

Scratch Pad Register (Read/Write)

Generally an RS flip-flop is used as basic memory
cell 1 bit read/write.

4-Byte RAM Register File

M-Byte RAM Register File

Number of
registers :M = 2n
Where n is number
of address lines.

RAM Read operation

RAM Write operation

RAM - Types
DRAM
SRAM

ROM - Types
PROM
EPROM
EEPROM

Example of PROM

Microcontroller V/S Microprocessor

Harvard
RISC

Von Neumann
CISC

Harvard v/s von Neumann Block

Architectures

PIC Microcontroller 16F877A.

16F877A
Block - Diagram

DATA TRANSFER UNIT

A set of functional elements linked together to facilitate a
variety of data transfer is called Data Transfer Unit (DTU).
1. RE Read Enable
2. WE Write Enable
3. RCLK RAM write Clock
4. RAWE RAM Address Write Enable
5. RAMACLK RAM Address Clock
6. WR Working register Read
7. WW Working register Write
8. WCLK - Working register Write Clock
9. OWE Output Write Enable
10. OE Output Enable
11. OCLK Output Clock
12. IE Input Enable
13. ICLK Input Clock

RAM File Registers

Data Bus (8)
RE
WE

RAM file
registers (368 8)

RCLK

RAM address
decoder
RAM address
register

RAMACLK

RAWE
Memory Address (9)

RAM File Registers Write Operation

Data Bus (8)
Data

WE

RAM file
registers (368 8)

RCLK

RAM address
decoder
RAM address
register

RAMACLK

RAWE
Memory Address (9)

RAM File Registers Read Operation

Data Bus (8)
Data

RE

RAM file
registers (368 8)
RAM address
decoder
RAM address
register

RAMACLK

RAWE
Memory Address (9)

Input Port

Data Bus
IE
Input register

Input

ICLK

Output Port

Output
OE
Output register
OWE

Data Bus

OCLK

Working Register

Output
WR
Working register
WW

WCLK

Input
Data Bus

Working Register - Write

Working register
WW

WCLK

Input
Data Bus

Working Register - Read

Data Bus
Output
WR
Working register

DTU Operation and Clock Generation

The DTU as a whole has 13 control signals.
Five of these are clock signals used to load data
into the respective registers.
These can be generated from a single clock signal
as shown below.

DTU Operations
Status of control lines
Sl. RAWE RE WE I OWE
E
No.
01
0
0
0
1
0

WW WR

02

03

04

05

06

07

Activity
Transfer data from input port to
working register
Write address into RAM address
register (get ready to select an
address location in the register file)
Transfer data from working register
into the selected RAM location
Transfer data from working register
to the output port
Transfer data from selected RAM
location into the working register
Transfer data from selected RAM
location into the output port
Transfer data from input port to the
selected RAM location

Enhanced DTU

Enhanced DTU With addition of ALU

Opcode and Program

Program -A set of instructions for a computer to
perform a specific task.
An instruction set, or command set, is the basic set of
commands understood by the microcontroller.
Instruction set is unique for a microcontroller.
Instruction consists of a mnemonic a keyword and
data / address ( In some cases only mnemonic).
- movlw 0x76 movlw - keyword, 0x76 data
- movwf 0x24 movwf - keyword, 0x24 - addr
- Clrw Only key word
For each keyword we have a unique binary bit pattern
known as Opcode Operation Code

Program Execution
Once an instruction sequence (program) is
prepared and loaded into the PM, the EDTU is
ready for operation: The operational sequence
is as follows:
PC is initialized and points to the location
where the first instruction to be executed is
stored
The instruction is fetched and loaded into the
instruction register; this constitutes the fetch
cycle phase of instruction execution

Program Execution (Contd)

The instruction in the instruction register is decoded
by the instruction decoder and executed; this
constitutes the execution phase of instruction
execution.
PC is incremented. The instruction fetch operation
during fetch cycle and execute operation during
execute cycle are carried out for the second
instruction.
The PC is again incremented, the third instruction
fetched and executed and so on.

Program Execution (Contd)

The instruction fetch and execute cycles
together is called a Machine Cycle. Thus
program execution is a sequence of machine
cycles carried out as desired.
Process continues till the last instruction of the
program.

Processor operation timing and sequence

Processor operation timing and sequence

The clock has 4 phases designated 1, 2, 3
and 4.
Four successive clock pulses together represent
an interval in which an instruction can be
fetched or executed. It is called the instruction
cycle.
As such a machine cycle fetch and execute
operations together lasts for 2 instruction
cycles or 8 clock periods.
Parallel processing takes place Hence while
executing ith instruction (i+1)th instruction can
be fetched. ( Harvard Architecture )