The Transistor Revolution

First transistor
Bell Labs, 1948
Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

The First Integrated Circuits

Bipolar logic
1960s

ECL 3-input Gate

Motorola 1966
Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

1975

1974

1973

1972

1971

1970

1969

1968

1967

1966

1965

1964

1963

1962

1961

1960

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

1959

LOG2 OF THE NUMBER OF

COMPONENTS PER INTEGRATED FUNCTION

Moores Law

Electronics, April 19, 1965.

Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

Silicon IC processing
Similar to photographic printing
Expose the silicon wafer through a mask
Process the silicon wafer
Repeat sequentially to pattern all the layers
Layout: A set of masks that tell a fabricator what

to pattern
For each layer in your circuit
Layers are metal, drain/source implants, gate, etc.
You draw the layers
Subject to vendor-supplied spacing rules

Lecture 5: IC Fabrication

The wafer
Czochralski process

Melt silicon at 1425 C

Add impurities (dopants)
Spin and pull crystal
Slice into wafers

0.25mm to 1.0mm thick

Polish one side

Lecture 5: IC Fabrication

Lecture 5: IC Fabrication

Crystal and wafer

Wand
(a finished 250lb crystal)
Lecture 5: IC Fabrication

A polished wafer

The mask
Illuminate reticle on

wafer
Typically 4 reduction

4X reticle

Typical image is

2525mm
Limited by focus

Wafer

Step-and repeat across

wafer
Limited by mechanical
alignment

Lecture 5: IC Fabrication

Lithography
Patterning is done by exposing photoresist with

light
Requires many steps per layer
Example: Implant layer

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

10

Grow Oxide Layer

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

11

Add Photoresist

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

12

Mask

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

13

Animation

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

14

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

15

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

16

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

17

Lecture 5: IC Fabrication

Reference: FULLMAN KINETICS

18

Lecture 5: IC Fabrication

9/03 IEEE spectrum

19

Patterning
How we pattern

and expose the

resist
To make the
patterns we want on
the silicon

IEEE Spectrum, 7/99, p. 41

Lecture 5: IC Fabrication

20

Lecture 5: IC Fabrication

9/03 IEEE spectrum

21

Detailed process sequence

1. Grow epi layer
Ultra-pure singlecrystal silicon

2. Implant n-well

Lecture 5: IC Fabrication

22

Detailed process sequence (cont)

3. Define active area

4. Grow field oxide

For isolation

Lecture 5: IC Fabrication

23

Detailed process sequence (cont)

5. Grow gate oxide

6. Pattern polysilicon

Lecture 5: IC Fabrication

24

Detailed process sequence (cont)

7. Form pFETs

8. Form nFETs

Lecture 5: IC Fabrication

25

Detailed process sequence (cont)

9. Deposit LTO by CVD

LTO is low-temperature
oxide
CVD is chemical vapor
deposition

10. Deposit Metal1

Usually aluminum

Lecture 5: IC Fabrication

26

Detailed process sequence (cont)

11. Via definition
Deposit LTO
Make via cuts

12. Deposit Metal2

Usually aluminum

13. Overglass (not shown)

Coat entire chip with Si3N4
Make pad openings in
Si3N4
Lecture 5: IC Fabrication

27

An inverter

Lecture 5: IC Fabrication

28

A Pentium cutaway
Figure courtesy
Yan Borodovsky,
Intel

Lecture 5: IC Fabrication

29

National 0.18m process cutaway

Lecture 5: IC Fabrication

30

Advanced Metallization - Copper

Lecture 5: IC Fabrication

Copper versus Aluminum

~ 40% lower resistivity
~ 10 less electromigration

31

Interconnect Impact on Chip

Lecture 5: IC Fabrication

32

Nature of Interconnect

No of nets
(Log Scale)

Local Interconnect

Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II

Global Interconnect
SGlobal = SDie

Source: Intel

SLocal = STechnology

10

100

1,000

10,000

100,000

Length (u)

Lecture 5: IC Fabrication

33

Lecture 5: IC Fabrication

34

Permittivity

Lecture 5: IC Fabrication

35

Lecture 5: IC Fabrication

36

Lecture 5: IC Fabrication

37

Lecture 5: IC Fabrication

38

Lecture 5: IC Fabrication

39

Projections

Simulated distribution of dopant

atoms in a 0.05m nFET
red: acceptor atom
blue: donor atom

All figures from IEEE Spectrum, 7/99

Lecture 5: IC Fabrication

40

An AMD 50nm transistor

Lecture 5: IC Fabrication

41

Frequency

Frequency (Mhz)

10000

Doubles every
2 years

1000
100
10

8085

1
0.1
1970

8086 286

386

486

P6
Pentium proc

8080
8008
4004
1980

1990
Year

2000

2010

Lead Microprocessors frequency doubles every 2 years

Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

Courtesy, Intel

42

Power Dissipation

Power (Watts)

100
P6
Pentium proc
10
8086 286
1

8008
4004

486
386

8085
8080

0.1
1971

1974

1978

1985

1992

2000

Year

Lead Microprocessors power continues to increase

Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

Courtesy, Intel

43

Power density
Power Density (W/cm2)

10000
1000
100

Rocket
Nozzle
Nuclear
Reactor

8086
10 4004
Hot Plate
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year

Power density too high to keep junctions at low temp

Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

Courtesy, Intel

44

10,000
10,000,000

100,000
100,000,000

Logic Tr./Chip
Tr./Staff Month.

Complexity

1,000
1,000,000

10,000
10,000,000

100
100,000

Productivity
(K) Trans./Staff - Mo.

Logic Transistor per Chip (M)

Productivity Trends

1,000
1,000,000
58%/Yr. compounded
Complexity growth rate

10
10,000

100
100,000

1,0001

10
10,000
x

0.1
100

xx

0.01
10

xx
x

1
1,000

21%/Yr. compound
Productivity growth rate

0.1
100
0.01
10

2009

2007

2005

2003

2001

1999

1997

1995

1993

1991

1989

1987

1985

1983

1981

0.001
1

Source: Sematech

Complexity outpaces design productivity

Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

Courtesy, ITRS Roadmap

45

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area

Lecture 5: IC Fabrication

46

NRE Cost is Increasing

Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

47

Die Cost

Single die

Wafer

Going up to 12 (30cm
Lecture 5:Digital
IC Fabrication
Rabaey:
Integrated Circuits2nd

From http://www.amd.com

48