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# Counters

Pendahuluan

Frequency Division
A frequency divider can be
constructed from J-K flip-flops
by taking the output of one cell
to the clock input of the next.
The J and K inputs of each
flip-flop are set to 1 to produce
a toggle at each cycle of the
clock input.
For each two toggles of the
first cell, a toggle is produced
in the second cell, so its
output is at half the frequency
of the first.
The output of the fourth cell is
1/16 the clock frequency. The
same device is useful as a
binary counter.

Binary Counting
A binary counter can be
constructed from J-K flip-flops
by taking the output of one cell
to the clock input of the next.
The J and K inputs of each flipflop are set to 1 to produce a
toggle at each cycle of the clock
input.
For each two toggles of the first
cell, a toggle is produced in the
second cell, and so on down to
the fourth cell.
This produces a binary number
equal to the number of cycles of
the input clock signal. This
device is sometimes called a
"ripple through" counter.
The same device is useful as a
frequency divider.

Counters

## Binary count sequence

Asynchronous counters
Synchronous counters
Aplikasi

## Binary count sequence

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Asynchronous counters

Asynchronous counters

Asynchronous counters

Synchronous counters

Synchronous counters

Synchronous counters

Synchronous counters

Synchronous counters

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Example

Example

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## A BCD counter or decade counter can be constructed

from a staight binary counter by terminating the "ripplethrough" counting when the count reaches decimal 9
(binary 1001).
Since the next toggle would set the two most significant
bits, a NAND gate tied from those two outputs to the
asynchronous clear line will start the count over after 9.

Counter
The 14-pinand
7490 Decoder
counter chip and the 16-pin

## decoder chip are often used together to drive

7-segment displays.

Frequency Counter
A frequency counter can
binary counter and a
decoder/display unit.
In the schematic below an
AND gate is used as an
input device. The unknown
frequency is applied to
one input of the AND and
sample pulses of precise
time interval are applied to
the other.
When the sample pulse is
high, the input signal is
transferred to the counter.
The number of counts divided
by the sample time interval
gives the frequency.

Frequency Counter
In the design shown,
there is another practical
element: after the count
is done, there must be
time to view the result on
the display, so a third
input to the AND gate is
taken from a J-K flip-flop.
The input reaches the
counter only when both
the sample pulse and the
J-K flip-flop are high
(counts are collected on
alternate sample pulses).
This provides an interval
when the frequency is
displayed. On each
positive-going edge of
the J-K, a
one-shot multivibrator is
triggered to send a pulse
for resetting the counter.

Shift Register

## Binary data can be shifted

from one flip-flop to the next
on each clock pulse.
The shift from left to right
here is the kind of
data transfer that occurs in a
serial transfer.

## Data Handling Systems

Both data about the physical world and control signals sent
to interact with the physical world are typically "analog" or
continuously varying quantities.
In order to use the power of digital electronics, one must
convert from analog to digital form on the experimental
measurement end and convert from digital to analog form
on the control or output end of a laboratory system.

Analog-to-Digital Conversion
This is a sample of the large number of analog-to-digital
conversion methods.
The basic principle of operation is to use the comparator
principle to determine whether or not to turn on a particular
bit of the binary number output.
It is typical for an ADC to use a digital-to-analog converter (
DAC) to determine one of the inputs to the comparator.

Conversion from
analog to digital form
inherently involves
comparator action
where the value of the
analog voltage at
some point in time is
compared with some
standard.
A common way to do
that is to apply the
analog voltage to one
terminal of a
comparator and
trigger a
binary counter which
drives a DAC.
The output of the DAC is applied to the other terminal of the comparator.
Since the output of the DAC is increasing with the counter, it will trigger
the comparator at some point when its voltage exceeds the analog input.
The transition of the comparator stops the binary counter, which at that
point holds the digital value corresponding to the analog voltage.

Illustration of 4-bit SAC with 1 volt step size (after Tocci, Digital Systems).

is much faster than the digital ramp
ADC because it uses digital logic to
converge on the value closest to the
input voltage.
A comparator and a DAC are used
in the process.

llustrated is a 3-bit flash ADC with
resolution 1 volt (after Tocci).
The resistor net and comparators
provide an input to the combinational
logic circuit, so the conversion time is
just the propagation delay through the
network - it is not limited by the clock
rate or some convergence sequence.
It is the fastest type of ADC available,
but requires a comparator for each
value of output (63 for 6-bit, 255 for 8bit, etc.)
Such ADCs are available in IC form
up to 8-bit and 10-bit flash ADCs
(1023 comparators) are planned.
The encoder logic executes a truth
table to convert the ladder of inputs to
the binary number output.

Digital-to-Analog Conversion
When data is in binary form, the 0's and 1's may be of
several forms such as the TTL form where the logic zero
may be a value up to 0.8 volts and the 1 may be a voltage
from 2 to 5 volts.
The data can be converted to clean digital form using
gates which are designed to be on or off depending on the
value of the incoming signal. Data in clean binary digital
form can be converted to an analog form by using a
summing amplifier.
For example, a simple 4-bit D/A converter can be made
with a four-input summing amplifier.
More practical is the R-2R Network DAC.

## Four-Bit D/A Converter

One way to achieve D/A conversion is to use a summing amplifier.

## This approach is not satisfactory for a large number of bits because it

requires too much precision in the summing resistors. This problem is
overcome in the R-2R network DAC.