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Outline
Memory Interfacing
Address size expansion
Word size expansion
Timing Analysis
Basic Concepts
A memory device can be viewed as a
single column table.
Table index (row number) refers to
the address of the memory.
Table entries refer to the memory
contents or data.
Each table entry is referred as a
memory location or as a word.
Memory Address
Binary
Hex
Memory
Contents
00-0000-0000
00-0000-0001
000
001
10011001
00111000
00-0000-0010
00-0000-0011
002
003
11001001
00111011
11-1111-1100
11-1111-1101
3FC
3FD
01101000
10111001
11-1111-1110
3FE
00110100
11-1111-1111
3FF
00011000
Address Lines
A memory device or memory chip must have
three types of lines or connections: Address,
Data, and Control.
Address Lines: The input lines that select a
memory location within the memory device.
Decoders are used, inside the memory chip, to
select a specific location
The number of address pins on a memory chip
specifies the number of memory locations.
If a memory chip has 13 address pins
(A0..A12), then it has:
213 = 23 X 210 = 8K locations.
If a memory chip has 4K locations, then it
should have N pins:
2N = 4K = 22 X 210 = 212 N=12 address pins
(A0..A11)
A00
A01
An-2
An-1
Y00
Y01
Y02
Y03
Location 000
Location 001
Location 002
Location 003
YFC
YFD
YFE
YFF
Location 0FC
Location 0FD
Location 0FE
Location 0FF
Data Lines
Data Connections: All memory devices have a set of data output pins (for ROM
devices), or input/output pins (for RAM devices).
Most RAM chips have common bi-directional I/O connections.
Most memory devices have 1, 8 or 16 data lines.
Data Input Lines
(DI0..DIn-1)
k- address lines
(A0..Am-1)
2m words
Read (RD)
Write (WR)
n-bits per
word
k- address lines
(A0..Am-1)
2m words
k- address lines
(A0..Am-1)
2m words
Read/Write (R/W)
Chip Select (CS)
n-bits per
word
n-bits per
word
Data Input/Output
Lines (D0..Dn-1)
(2m X n) RAM with common I/P
and O/P Data lines
Control Lines
Enable Connections:
All memory devices have at least one Chip Select (CS) or Chip Enable (CE)
input, used to select or enable the memory device.
If a device is not selected or enabled then no data can be read from, or
written into it.
The CS or CE input is usually controlled by the microprocessor through
the higher address lines via an address decoding circuit.
Control Connections:
RAM chips have two control input signals that specify the type of memory
operation: the Read (RD) and the Write (WR) signals.
Some RAM chips have a common Read/ Write (R/W) signal.
ROM chips can perform only memory read operations, thus there is no need
for a Write (WR) signal.
In most real ROM devices the Read signal is called the Output Enable
(OE) signal.
Some of the address lines select the memory devices that owns the memory location
to be read (Step 1a), while the rest point to the required memory location within the
memory device.
The processor activates the Read (RD) signal (Step 2).
The selected memory device loads on the data bus the content of the memory
location specified by the address bus (Step 3).
The processor reads the data from the data bus, and resets the RD signal (Step 4).
Clock
T1
Address Bus
T2
T3
Valid Address
Chip Enable
Read (RD)
Data Bus
Invalid Data
Step 1a
Step 1
Step 2
Valid Data
Step 3
Step 4
Some of the address lines select the memory devices that owns the memory location
to be written (Step 1a), while the rest point to the required memory location within
the memory device.
The processor loads on the data bus the data to be written (Step 2).
The processor activates the Write (WR) signal (Step 3).
The data at the data bus is stored in the memory location specified by the address
bus (Step 4).
Clock
T1
T2
Address Bus
T3
Valid Address
Data Bus
Valid Data
Chip Enable
Write (WR)
Step 2
Step 1
Step 1a
Step 3
Step 4
Used to store
Programs such as the BIOS.
Data such as look tables
e.g. the bit pattern of the
characters in a dot matrix
printer.
Used to store
A0
A1
A2
CS
3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7
A0
A1
A2
CS
OE
OE
D3
D2
D1
D0
3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7
D3
D2
D1
D0
A0
A1
A2
CS
3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7
OE
D3
D2
D1
D0
(2Kx8)
2732/27C16
(4Kx8)
2764/27C64
(8Kx8)
27128/27C128
(16Kx8)
27256/27C256
(32Kx8)
27512/27C512
(64Kx8)
27010/27C010
(128Kx8)
271024/27C1024
27020/27C020
(256Kx8)
272048/27C2048 (128Kx16)
27040/27C040
(512Kx8)
274096/27C4096 (256Kx16)
(64Kx16)
RAM Cells
Static RAM (SRAM):
The basic element of a static RAM cell is the D-Latch.
Data remains stored in the cell until it is intentionally
modified.
SRAM is fast (Access time: 1ns).
SRAM needs more space on the semiconductor chip
than DRAM.
SRAM more expensive than DRAM
SRAM needs more space than DRAM
Bit Select
Data In
Data Out
Data Out
Data In
Write
En
RAM Cell
DRAM Cell
(2Kx8)
6164/6264
(8Kx8)
61256/62256
(32Kx8)
611024/621024 (128Kx8)
These series of SRAM devices are pin compatible with the 27XXX series of
EPROMs, with the difference that the WR signal is replaced by the programming
voltage pin (Vpp) on the EPROM. This allows a single socket on the PCB hold either
a SRAM, during system development, or an EPROM, after the operation of the
program is verified to be the expected one.
Static RAM is fast with access times much less than 100ns. SRAM chips with access
times less than 10ns are often used as cache memory in computers.
DYNAMIC RAM
DRAM requires refreshing every 2 to 4 ms .
Refreshing occurs automatically during a read or write.
Internal circuitry takes care of refreshing cells that are not accessed over this interval.
For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256).
For the 8086, a read or write occurs every 800ns .
This allows 19 memory reads/writes per refresh or 5% of the time.
DRAM technologies
EDO DRAM
SDRAM
DRDRAM
DDR DRAM
Soft errors occur on DRAMs which often require ERROR DETECTION and/or ERROR
CORRECTION
A DRAM CONTROLLER is required for using DRAM
A reasonable rule of thumb is to expect one bit error, per month, per
gigabyte of memory
Systems often use error detection and correction methods to identify and
possibly correct soft errors
repetition schemes
parity schemes (74AS280)
cyclic redundancy checks
Hamming distance based checks (74LS636)
Disadvantages:
Cannot correct errors, only detect them
Only detects an odd number of errors
PARITY EXAMPLE
Calculate the parity bit for both even and odd parity, for the following sequence
1001
0001
1000
1000011
Assuming that the last bit is the parity bit (odd parity), determine which data transmission was
successful and which unsuccessful
10001010
00111011
11011101
EXAMPLE
Design the majority voting circuit for one memory bit
DRAM CONTROLLER
A circuit performing address multiplexing and DRAM control signal generation
Memory Expansion
Using 4 SIMMs on
the Motherboard
Memory Expansion
using 4 Memory
Chips on a SIMM
Motherboard
Slot 3
Slot 4
Slot 1
Slot 2
SIMM
SIMM
SIMM
Processor
Address Size Expansion: (32X4 RAM module using 8X4 RAM chips)
D0
D1
D2
D3
RAM1
RD
WR
A0
A1
A2
A3
A4
A5
A6
D3
RAM2
D3
D 0
RAM3
D 3
D0
RAM4
D 3
RD
WR
Y0
Y1
B
CS
Address
Selection
D 0
CS
RD
Y2
Y3
2X4 DEC.
WR
CS
RD
WR
CS
RD
WR
D 0
CS
Memory Maps
Tables that show the addresses occupied by each memory device in a system.
In the previous example it is assumed
that the processor has only 7 address
line, thus it can address 128 memory
locations.
The size of the RAM memory
module is 32 bytes, thus the module
can be mapped to occupy one out of
the four available memory blocks in
the memory map.
The memory block occupied by the
memory module depends on the
connection of the address selection
circuit (AND gate) that enables the
decoder.
A5
A6
A5
A6
00 - 07
RAM
08 - 0F
RAM
10 - 17
RAM
18 - 1F
RAM
20 - 3F
40 - 5F
60 - 7F
Not
Used
Not
Used
Not
Used
00 - 1F
A5
A6
Not
Used
20 - 27
RAM
28 - 2F
RAM
30 - 37
RAM
38 - 3F
RAM
40 - 5F
60 - 7F
Not
Used
Not
Used
A5
A6
00 - 1F
Not
Used
20 - 3F
Not
Used
40 - 47
RAM
48 - 4F
RAM
50 - 57
RAM
58 - 5F
RAM
60 - 7F
Not
Used
00 - 1F
Not
Used
20 - 3F
Not
Used
40 - 5F
Not
Used
60 - 67
RAM
68 - 6F
RAM
70 - 77
RAM
78 - 7F
RAM
Address Selection
Circuit
A6
0
0
0
A5
0
0
0
A4
0
0
0
A3
0
0
1
A2
0
1
0
A1
0
1
0
A0
0
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
A5
A6
Address Selection
Circuit
A 6 A 5 A 4 A 3 A 2 A 1 A 0 Mem. Map
0 0 0 0 0 0 0 00
Not
Used
0 0 1 1 1 1 1 1F
1
0
1
Mem. Map
00
RAM1
07
08
RAM2
0F
10
RAM3
17
18
RAM4
1F
0
1
20
7F
Not
Used
A5
A6
Address Selection
Circuit
A6
0
0
1
A5
0
1
0
A4
0
1
0
A3
0
1
0
A2
0
1
0
A1
0
1
0
A0
0
1
0
A6
0
1
1
A5
0
0
1
A4
0
1
0
A3
0
1
0
A2
0
1
0
A1
0
1
0
A0
0
1
0
1
1
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
Mem. Map
00
Not
Used
3F
40
RAM1
47
48
RAM2
4F
50
RAM3
57
1
1
1
1
1
1
0
1
1
1
0
0
1
0
1
1
0
1
1
0
1
Mem. Map
00
Not
Used
5F
60
RAM1
67
68
RAM2
6F
70
RAM3
77
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
78
7F
20
0
0
0
1
1
1
0
0
0
0
1
1
1
0
1
1
0
1
1
0
1
27
28
2F
0
0
1
1
1
1
0
0
0
1
0
1
0
1
30
37
RAM3
0
0
1
1
1
1
1
1
0
1
0
1
0
1
38
3F
RAM4
1
1
0
0
1
1
1
1
0
1
0
1
0
1
58
5F
RAM4
1
1
0
1
0
1
0
1
0
1
0
1
0
1
40
7F
Not
Used
1
1
1
1
0
1
0
1
0
1
0
1
0
1
60
7F
Not
Used
RAM1
RAM2
A5
A6
Address Selection
Circuit
RAM4
Example: (32X4 RAM module using 8X4 RAM chips - Assume an 8-address line processor)
D3
D0
D3
D0
D3
D0
8x4 RAM 4
A0
A2
A2
A2
A2
WR
CS
2X4 DEC.
A
B
A5
A7
D0
8x4 RAM 3
A0
A0
A6
D3
8x4 RAM 2
A0
RD
WR
A3
A4
D0
8x4 RAM 1
A0
RD
A2
D3
Y0
Y1
Y2
CS
Y3
RD
WR
CS
RD
WR
CS
RD
WR
CS
Address Selection
Circuit
A5
A6
A7
Address Selection
Circuit
A5
A6
A7
Address Selection
Circuit
A5
A6
A7
A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
0 0 0 0 0 0 0 0 00
RAM1
0 0 0 0 0 1 1 1 07
A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
0 0 0 0 0 0 0 0 00 Not
1 0 0 1 1 1 1 1 9F Used
A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
0 0 0 0 0 0 0 0 00 Not
1 1 0 1 1 1 1 1 DF Used
0 0 0 0 1 0 0 0 08
RAM2
0 0 0 0 1 1 1 1 0F
1 0 1 0 0 0 0 0 A0
RAM1
1 0 1 0 0 1 1 1 A7
1 1 1 0 0 0 0 0 E0
RAM1
1 1 1 0 0 1 1 1 E7
0 0 0 1 0 0 0 0 10
1 0 1 0 1 0 0 0 A8
1 1 1 0 1 0 0 0 E8
RAM3
0 0 0 1 0 1 1 1 17
0 0 0 1 1 0 0 0 18
RAM4
0 0 0 1 1 1 1 1 1F
1 0 1 0 1 1 1 1 AF
1 0 1 1 0 0 0 0 B0
RAM3
1 0 1 1 0 1 1 1 B7
RAM2
1 1 1 0 1 1 1 1 EF
1 1 1 1 0 0 0 0 F0
RAM3
1 1 1 1 0 1 1 1 F7
0 0 1 0 0 0 0 0 20
1 0 1 1 1 0 0 0 B8
1 1 1 1 1 0 0 0 F8
Not
1 1 1 1 1 1 1 1 FF Used
1 0 1 1 1 1 1 1 BF
1 1 0 0 0 0 0 0 C0
RAM2
RAM4
Not
Used
1 1 1 1 1 1 1 1 FF
1 1 1 1 1 1 1 1 FF
RAM4
Design Example:
Design an 8KX8 RAM module using 2KX8 RAM chips. The module should be connected on
an 8-bit processor with a 16-bit address bus, and occupy the address range starting from the
address A000. Show the circuit and the memory map.
Number of memory devices needed = 8K/2K
=4
Decoder needed = 2X4
Number of address lines on each 2KX8
memory chip = 11
2m = 2K = 21 x 210 = 211 (A0..A10)
Decoder needed = 2X4
2 address lines are needed for the decoder.
(A11..A12)
Number of address lines needed for the
address selection circuit
= 16 - 11 - 2 = 3 (A13, A14 A15)
Circuit Diagram
D7
D0
D7
2Kx8 RAM
D0
2Kx8 RAM
A13
A14
A15
A15
D7
2Kx8 RAM
D0
A0
A10
A10
A10
A10
WR
CS
Y0
Y1
Y2
CS
Y3
RD
WR
CS
RD
WR
D7
2Kx8 RAM
A0
2X4 DEC.
A12
D0
A0
RD
WR
A11
D7
A0
RD
A0
D0
CS
RD
WR
CS
Address Decoding
The physical address space, or memory map, of a microprocessor refers to the range
of addresses of memory location that can accessed by the microprocessor. The size of
the address space depends on the number of address lines of the microprocessor.
At least two memory devices are required in a microprocessor system: one for the
ROM and one for the RAM.
In an 8088/8086 the high addresses in the memory map should always be occupied
by a ROM, while the low addresses in the memory map should always be occupied
by a RAM.
Address decoding is required in order to enable the connection of more than one
memory devices on the microprocessor. Each device will occupy a unique area in the
memory map.
A memory system is not fully decoded if some of the address lines are not used by
the address decoding circuit or memory. In this case a memory device will occupy
more than one sections in the memory map. This is referred as memory mirroring or
memory imaging.
An address decoding circuit must ensure that an address section is occupied by only
one memory device. If two or more devices occupy the same addresses then bus
contention will occur. Bus contention occurs if two of more devices drive the bus at the
same time. Bus contention can be either static or dynamic.
Static bus contention occurs when two or more devices drive a bus for a prolonged
time period. This might damage some of the components of the system. Static bus
contention might be caused by improper address decoding design, or by other faults
in the system such as a short circuit of the CS of a device to the ground.
Dynamic bus contention occurs when two or more devices drive a bus for a short
period of time. This might change the logic levels on the bus and cause system
malfunctions.Dynamic bus contention might be caused by improper address
decoding design, or by wrong memory timing analysis.
A
A
A
A
A
0
14
MEM 1
CS
A
A
0
14
MEM 2
CS
19
18
17
16
15
14
Memory Map
28000H
2FFFFH
16
40000H
17
47FFFH
15
18
19
MEM1
MEM2
0
14
3X8 Dec.
A
A
A
A
A
15
16
17
18
19
A
B
C
CS
Y
Y
0
1
Mem 1
Mem 2
Mem 8
CS
CS
CS
19
18
17
16
15
14
Memory Map
40000H
47FFFH
48000H
4FFFFH
78000H
7FFFFH
MEM1
MEM2
MEM8
PAL Programming
PAL
16L8
A
A
A
A
A
1
15
16
17
18
19
2
3
4
5
6
I1
I2
I3
I4
I5
I6
I 10
Mem 1
Q
Q
19
1
18
CS
CS
Mem 8
12
8
20
10
CS
Vcc
Gnd
19
18
17
16
15
14
Memory Map
40000
47FFF
48000
;11 12 13 14 15 . . . . 18 19 20
NC Q8 Q7 Q6 Q5 . . . Q2 Q1 Vcc
4FFFF
EQUATIONS
78000
7FFFF
Mem1
Mem2
Mem8
A
A
A
A
MEM 1
15
CS
MEM 2
15
CS
X=Y
X1 X2 X3 X
+5V
Gnd
A
A
A
A
16
17
18
19
X=Y
Y1 Y2 Y3 Y
X1 X2 X3 X
A
Y1 Y2 Y3 Y
19
18
17
16
15
Memory Map
90000
9FFFF
C0000
CFFFF
MEM1
MEM2
Solution:
62256 SRAM chips:
256/8 =32 32KX8
Number of chips needed:
128K/32K = 4
Number of address lines:
32K = 25K = 25 * 210 = 215
15 address lines (A0 .. A14)
19
18
17
16
15
14
13
Memory Map
C0000
C7FFF
C8000
CFFFF
D0000
D7FFF
D8000
DFFFF
RAM1
RAM2
RAM3
RAM4
62256
14
8088 System
RD
RD
WR
A
A
IO/M'
19
A
A
A
A
A
15
16
17
18
19
WR
62256
D
CS
14
RD
WR
62256
D
CS
14
RD
WR
62256
D
CS
14
RD
WR
CS
62256
14
8088 System
RD
RD
WR
A
A
IO/M'
19
A
A
A
A
A
17
18
19
15
16
WR
LS139
A Y0
B Y1
Y2
E
Y3
62256
D
CS
14
RD
WR
62256
D
CS
14
RD
WR
62256
D
CS
14
RD
WR
CS
62256
14
8088 System
RD
RD
WR
A
A
IO/M'
19
WR
62256
D
CS
14
RD
WR
X=Y
X
A
A
A
A
A
Gnd
+5V
15
16
17
18
19
62256
D
CS
14
RD
WR
X=Y
Y
62256
D
CS
14
RD
WR
X=Y
Y
CS
X=Y
Y
Homework:
Show how a 32Kbyte ROM module can be connected on an 8088 system using 2764
EPROM chips, occupying the address range starting from the address E0000H. Use
the following address decoding circuits:
1
2
3.
4.
5
Solution:
Size of 2764 EPROM chips:
19
18
17
16
15
14
13
12
11
Memory Map
2764
A0
D0
D0
A 12
8088 System
OE
D7
RD
WR
A0
A19
IO/M'
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
D0
A 12
8088 System
OE
D7
RD
WR
A0
A19
IO/M'
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
D0
A 12
8088 System
OE
D7
RD
WR
A0
A19
IO/M'
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
D0
A 12
8088 System
OE
D7
RD
WR
A0
A19
IO/M'
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
D0
A 12
8088 System
OE
D7
RD
WR
A0
A19
IO/M'
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
The memory is separated into the High Bank (odd addresses) and the Low Bank (even addresses).
The 8086 microprocessor can access either the low bank (D0..D7), or only the high bank (D8..D15),
or both banks (D0..D15).
The is a need only for separate Bank Write Strobes. When the processor reads from the memory,
it always reads both banks, and selects the necessary bank internally.
8086 System
D8
D7
D0
RD
WR
62256
A0
A15 A14
A1
D0
D7
A15
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
A1
62256
A0
A15 A14
A1
D0
D7
A15
RD WR CS
A0
Y0
A19
BHE'
A1
Y1
Y2
Y3
Y0
1E
LS139
A
Y1
Y2
Y3
LS139
B
IO'/M
A16 A17
A16 A17
A18 A19 A0
A18 A19
1E
62256
A0
D0
A14
D7
RD WR CS
D15
8086 System
D8
D7
D0
RD
A1
A15
62256
A0
D0
A14
D7
A1
A15
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
BHE'
WR
A0
A1
Y0
Y1
Y2
Y3
LS139
A
1E
A19
IO'/M
A16 A17
A18
A19
A1
A15
62256
A0
D0
A14
D7
RD WR CS
A1
A15
62256
A0
D0
A14
D7
RD WR CS
A2
80386 Processor
A16
D31
62256
D0
A0
D0
A14
D7 D7
RD WR CS
A2
A16
62256
D8
A2
A0
D0
A14
D7 D15
A16
Y0
Y2
RD WR CS
62256
A0
D0
A14
D7 D23
RD WR CS
RD
WR
BE0'
BE1'
BE2'
BE3'
A2
Y1
Y3
LS139
A
1E
A17 A18
A31
IO'/M
A19
D16
A31
A2
A16
62256
D24
A0
D0
A14
D7 D31
RD WR CS
Address
Symbol
t acc
t dh
CS
High Z
t df
t cd
Data
Parameter
Limit
Min.
Unit
Typ.
Max.
250
450
ns
120
ns
t acc
t cd
t df
100
ns
t dh
100
ns
Example
You are asked to interface 8Kx8 bit ROM chips with the following data to a 8088
microprocessor:
Chip-select to output delay: 70ns(min)
120ns(typ)
180ns(max)
Address to output delay: 230ns(min)
340ns(typ)
450ns(max)
Chip deselect to output float:
80ns(typ)
100ns(max)
Address to output hold:
80ns(typ)
100ns(max)
Assume that buffers have a delay of 20 ns, and latches a delay of 35 ns. The delay of the
wires is 20 ns
A. Calculate the number of wait states (if needed)
B. Draw the corresponding memory read operation timing diagram
C. Calculate the number of chips required to create a 32Kbyte ROM
D. Specify the memory map starting from address F8000H
E. Draw the decoding circuit using NAND gates only
F. Draw the decoding circuit using a decoder and NAND gates