VLSI DESIGN

VLSI Design Cycle

VLSI Design cycle:

VLSI design cycle start with a formal
specification of a VLSI chip, follows a series of
steps, and eventually produces a packaged chip.

A simple VLSI design cycle:

1. System Specification
2. Functional design
3. Logic design
4. Circuit design
5. Physical design
6. Fabrication
7. Packaging, Testing and Debugging

VLSI Design Cycle

System Specification

Circuit Design

Architectural Design

Physical Design

Functional Design

Fabrication

Logic Design

Packaging
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System Specification
1. First step of design process is to lay down the specification
of the system.
2. High level representation of the system.
3.

Factors considered:
a) Performance
b) Functionality
c) Physical dimension
d) Design technique
e) Fabrication technology

4. It is a compromise between market requirements,

technological and economical viability.
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System Specification contd.

The end results are specifications of
1. Size
2. Speed
3. Power and
4. Functionality of the VLSI system
5. Basic architecture of the system are also specified,
such as
a) Floating point unit
b) RISC versus CISC system
c) Number of ALUs
d) Number and structure of the pipelines
e) Size of the cache, etc.

Functional Design
1. Main functional units of the system are identified
2. Identifies the interconnect requirements between
the units
3. The area, power and other parameters of each unit
are estimated
4. The behavioral aspects of the system are considered
not implementation specification
- multiplication needed but does not specify its
hardware
5.

The key idea is to specify behavior, in terms of

a) Input
b) Output
c) Timing of each unit
Without specifying the internal structure.

Functional Design contd.

1.

The outcome of functional design is usually a

timing diagram or other relationships between
units.

2.

This information leads to improvement of the

overall design process and reduction of
complexity of the subsequent phases.

3.

Functional design provides a quick emulation of

the system and allows fast debugging of the full
system.

Logic Design

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)

Design the logic, that is,

1.
Boolean expressions,
2.
control flow,
3.
word width,
4.
register allocation, etc.
The outcome is called an RTL (Register Transfer
Level) description.
RTL is expressed in a HDL (Hardware Description
Language), such as VHDL and Verilog.
This description can be used in simulation and
verification.

As this description consists of Boolean expressions,

so they can be minimized to achieve the smallest
logic design.

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X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)

Logic Design cont

Logic and RTL Simulation

Logical simulation is used for verifying the logical correctness
of a hardware design.
Modern HDLs are both simulatable and synthesizable.
RTL simulation is made by applying test vectors or by running
test benches
Logic Optimization
Logic optimization (a part of logic synthesis) is the process of
finding an equivalent representation of the specified logic
circuit under one or more specified constraints.
Generally, the circuit is constrained to minimum chip area
meeting a pre-specified delay.
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Logic Design cont

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)

Logic Synthesis
Logical synthesis is the process of translating an
abstract form of a desired circuit behavior into a design
implementation in terms of logic gates.
This process is carried out by automatic synthesis tools
with sophisticated algorithms.
The outcome of this logic synthesis is the netlist or
schematic.
The corresponding circuit hardware realization is carried
out by a synthesis tool through two common
approaches; namely, FPGA and ASIC.
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Circuit Design
1.
2.

3.
4.

The purpose of the circuit design is to develop a circuit

representation based on the logic design.
The Boolean expression can be converted into a circuit
representation by taking into consideration the speed and
power requirements of the original design.
Design the circuit including gates, transistors,
interconnections, etc. The outcome is called a netlist.
Circuit simulation is used to verify the correctness and
timing of component.

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Physical Design
1.
2.

The circuit representation of each component is

converted into geometric representation.
Convert the netlist into a geometric representation. The
outcome is called a layout.

3.

Connections between different components are also

expressed as a geometric pattern.

4.

Exact details depends upon design rules

5.

It is a complex process and usually broken down into

sub-steps.
Various verification and validation checks are performed
on the layout during physical design.

6.

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Layout tools
1.

Microwind layout tool: The following figure shows

conversion of the NAND gate circuit in to its equivalent
geometric pattern(layout).
-Other Layout tools includes Magic.

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Fabrication
1.

Fabrication: Process includes lithography, polishing,

deposition, diffusion, etc., to produce a chip.

2.

Fabrication process consists of several steps and

requires various masks.
Before the chip is mass produced, a prototype is made
and tested.

3.

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Packaging, Testing and Debugging

1.

2.

Packaging Put together the chips on a PCB

(Printed Circuit Board) or an MCM (Multi-Chip
Module)
Each chip is then packaged and tested to
ensure that it meets all the design
specifications and that it functions properly.

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VLSI Design Cycle

Netlist

System Specification

Physical
Design

Architectural
Design

Architectural
Specification
Functional
Design

Circuit Design
or
Logic Synthesis

Timing & relationship

between functional units
Logic
Design

RTL in HDL

Layout
Fabrication

Chips
Packaging

Packaged and
tested chips
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Physical Design Cycle

The input of the physical design cycle is a circuit
diagram and the output is the layout of the circuit.
Circuit Partitioning
Floorplanning & Placement
Routing
Layout Compaction
Extraction and Verification
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Circuit Partitioning
1.

A chip may contain several million transistors. So layout of

the entire circuit can not be handled due to the limitation
of memory space and computation power available.

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Circuit Partitioning contd.

2.
3.
4.

Partition a large circuit into sub-circuits (called

blocks).
Factors like #blocks, block sizes, interconnection
between blocks, etc., are considered.
The output of partitioning is a set of blocks and
the interconnections between them.

5. Partitioning may be hierarchical.

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Floorplanning

This step is concerned with selecting good layout for

each block as well as the entire chip.
The area of each block can be estimated after
partitioning based approximately on the number and type
of components of that block.
Interconnect area between blocks is also considered.
Done by design engineer rather than CAD tools: human is
better in visualization.
Certain components are often required to be located at a
specific position on the chip.

Deadspace
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Placement
1.
2.

The blocks are exactly positioned on the chip.

The goal is to minimize the area arrangement for the
blocks that allows completion of interconnections between
the blocks while meeting the performance constraints. For
example: routable blocks but fails timing goals.

Feedthrough
Standard cell type 1
Standard cell type 2

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Placement contd.
1.

2.

3.
4.

Two phases: initial placement is created in the

first phase. In second phase, initial placement is
evaluated and iterative improvements are made
until the layout has minimum area.
Quality of placement will not be evident until the
routing phase has been completed. Placement
may lead to an un routable design: More space
may be needed.
Good routing and circuit performance heavily
depends on a good placement algorithm.
This is due to the fact that after the position of
the block has been fixed, routing can do
nothing.
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Routing
1.
2.
3.

Objectives is to complete the interconnections between

modules.
Routing space is partitioned into channels and switchboxes.
Two phases : global routing and detailed routing.

Feedthrough
Type 1 standard cel1
Type 2 standard cell
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Global routing (GR)

1. In global routing, connections are completed between
proper blocks of the circuit disregarding exact
geometric details of each wire and pin.
2. For each wire GR finds a lists of channels which are to
be used as a passageways for that wire. In other
words, GR specifies different regions in the routing
space through which a wire should be routed.

Detailed routing (DR)

DR completes point-to-point connections between pins on
the blocks. GR is converted into exact routing by
specifying geometric information such as location and
spacing of wires and their layer assignments.
It includes channel and switchbox routing.
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Compaction & Verification

Compaction Compress the layout from all directions to
1.
2.
3.

minimize the total chip area. Advantages:

Making chip smaller, wire lengths are reduced.
Reduces signal delays.
More chip on a small area, so manufacturing cost reduced.

But should ensure design rules.

Verification Check the correctness of the layout. Include
DRC (Design Rule Checking), circuit extraction (generate a
circuit from the layout to compare with the original
netlist), performance verification, reliability verification.

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Review Physical Design

The final physical layout of a complicated circuit on a small piece

of silicon is generated in a set of steps using CAD tools

Partitioning
K-L and F-M Algorithms
Placement/
Floorplanning
Constructive &
K-L Algorithms
Routing

Break the circuit

up into smaller
segments

Place the segments

on the chip

Layout out the

wire paths
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Physical Design Algorithms

Partitioning
-Fiduccia-Mattheyses(FM)
-(Kernighan-Lin)KL, hMetis algorithms
Floor planning
Simulated annealing floor planning algorithms
Placement / Packing
Simulated annealing
Global / detailed routing
Maze routing, line-search, Steiner trees, channel routing

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