The World Leader in High Performance Signal Processing Solutions

A/D and D/A Conversion

Cosimo Carriero
Analog Dialogue Seminar
November 2011

Agenda
Fundamentals

of sampled data systems

A/D Converters Architectures
SAR
Sigma-Delta
Flash
Pipelined

D/A

Converters Architectures

Bit DAC
The Kelvin Divider or String DAC
Thermometer DAC
Binary-Weighted DAC
R-2R Ladder DAC
Segmented DAC
Oversampling Interpolating DAC
Multiplying DAC
A/D

and D/A Converters State of the Art

Imagine a world without ADCs

Sound
Light intensity
Temperature
Force
pH...
in other words...

...the Real
World
3

Sensor

Voltage
Current
Impedance
Time*
ADC

in other words...

...the Analog
World

Digital...
... storage
... display
... manipulation
... communication
in other words...

..the Digital
World

Analog vs. Digital Options

... back to the future
Analog

Digital

Storage

Magnetic tape
Chart recorder

Hard disk drive

Memory Card..

Display

Cathode Ray Oscilloscope

Moving coil meters
Optical indicators

Digital Oscilloscope
LCD Displays
7-segment display

Amplifiers
Analog Computers

Digital Signal
Processing

4-20mA loop
FM radio transmission

Ethernet
USB, GSM

(& retrieval !!!)

Manipulation
Communication

The World Leader in High Performance Signal Processing Solutions

Fundamentals of
Data Converters

Analog Devices Confidential 2008 Version 1a

Sampled Data System

fs

fa

LPF
OR
BPF

N-BIT
ADC

fs

DSP

AMPLITUDE
QUANTIZATION

LPF
OR
BPF

N-BIT
DAC

DISCRETE
TIME SAMPLING
fa

1
T s= f
s
t
t
6

Ts

2Ts

3Ts

4Ts

5Ts

6Ts

7Ts

Aliasing in the Time Domain

ALIASED SIGNAL = fs fa

INPUT = fa

1
fs
NOTE: fa IS SLIGHTLY LESS THAN fs

Sampling Theorem
If the Fourier Transform of a function f(t) is zero above a certain frequency c,
F() = 0 for || > c, then f(t) can be uniquely determined from its values

f n f n
c
at a sequence of equidistant points, distance /c, apart.
In fact f(t) is given by

f (t )

fn

sin c t n
c t n

Nyquist's Criteria
A signal with a maximum frequency fa must be sampled at a rate fs > 2fa or
information about the signal will be lost because of aliasing.
Aliasing occurs whenever fs < 2fa
A signal which has frequency components between fa and fb must be sampled
at a rate fs > 2 (fb fa) in order to prevent alias components from overlapping
the signal frequencies
The concept of aliasing is widely used in communications applications such as
direct IF-to-digital conversion.

Aliasing in the Frequency Domain

A

fa

0.5fs
1st Nyquist
Zone

fs
2nd Nyquist
Zone

1.5fs
3rd Nyquist
Zone

fs

2fs
4th Nyquist
Zone

fa

0.5fs

5th Nyquist
Zone

1.5fs

2.5fs

2fs

2.5fs

Aliasing in the Frequency Domain

A

fa

0.5fs
1st Nyquist
Zone

fs
2nd Nyquist
Zone

1.5fs
3rd Nyquist
Zone

2fs
4th Nyquist
Zone

2.5fs
5th Nyquist
Zone

0.5fs

fs

1.5fs

2fs

2.5fs

Oversampling Relaxes Requirements

on Baseband Antialiasing Filter
fa

fa

fs - fa

Kfs - f
a

DR

fs

fs

Kfs

2
STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to fs - fa

2
STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to Kfs - fa

CORNER FREQUENCY: fa

CORNER FREQUENCY: fa

Kfs

Quantization:
The Size of a Least Significant Bit (LSB)
RESOLUTION
N

VOLTAGE
(10V FS)

ppm FS

% FS

dB FS

2-bit

2.5 V

250,000

25

12

4-bit

16

625 mV

62,500

6.25

24

6-bit

64

156 mV

15,625

1.56

36

8-bit

256

39.1 mV

3,906

0.39

48

10-bit

1,024

9.77 mV (10 mV)

977

0.098

60

12-bit

4,096

2.44 mV

244

0.024

72

14-bit

16,384

610 V

61

0.0061

84

16-bit

65,536

153 V

15

0.0015

96

18-bit

262,144

38 V

0.0004

108

20-bit

1,048,576

9.54 V (10 V)

0.0001

120

22-bit

4,194,304

2.38 V

0.24

0.000024

132

24-bit

16,777,216

596 nV*

0.06

0.000006

144

*600nV is the Johnson Noise in a 10kHz BW of a 2.2k Resistor @ 25C

13

Remember: 10-bits and 10V FS yields an LSB of 10mV, 1000ppm, or 0.1%.

All other values may be calculated by powers of 2.

Quantization Noise as a Function of Time

Digital
output

e(t)
+q
2
SLOPE = s

analog
input

t
q = 1LSB

q
2

error

q
2s
ERROR =

e(t ) st

q
q
t
2s
2s

MEAN-SQUARE ERROR =

q q / 2s
q2
2
e (t )
( st ) dt

q
/
2
s
s
12
2

ROOT-MEAN-SQUARE ERROR =
1.14

erms e 2 (t )

q
12

+q
2s

Theoretical Quantization Noise

Ideal N-Bit Converter
Full _ Scale _ Sinewave _(rms )

Quantization _ Noise _(rms )

SNR 20 log10

q 2N
v(t ) V0 sin( t )
sin( t )
2
V0 q 2 N
v(rms )

2 2 2
q 2 N 12
3
SNR 20 log10

(
20

log
2
)

20

log

10
10
q
2
2

SNR (dB ) 6.02 N 1.76

ENOB

SNR (dB) 1.76

6.02

Quantization Noise Spectrum

NOISE
SPECTRAL
DENSITY

RMS VALUE =

q
12

q = 1 LSB

MEASURED OVER DC TO

fs
2

q / 12
fs / 2
fs
2

BW
SNR = 6.02N + 1.76dB + 10log
10

fs
2BW

Process Gain
1.16

FOR FS SINEWAVE

Basic ADC and DAC

SAMPLING
CLOCK

VDD VREF

EOC, DATA READY, ETC.

ANALOG
INPUT

DIGITAL
OUTPUT

ADC

VDD

VSS

(ANALOG INPUT)

GND
DIGITAL
INTPUT

18

VREF

DAC

VSS

GND

ANALOG
OUTPUT

Transfer Functions for Ideal 3-Bit DAC and ADC

DAC

FS

ADC
111
110

ANALOG
OUTPUT

DIGITAL
OUTPUT

101
100
011

QUANTIZATION
UNCERTAINTY

010

QUANTIZATION
UNCERTAINTY

001
000
000

001

010

011

100

101

DIGITAL INPUT

110

111

ANALOG INPUT

FS

Static (DC) Errors in Converters

FS

FS

ACTUAL

ACTUAL
IDEAL

OFFSET ERROR

IDEAL

GAIN ERROR

FS
0.5LSB
DNL=-0.5LSB

ACTUAL
IDEAL
LINEARITY ERROR

INTEGRAL LINEARITY ERROR

1.5LSB
DNL=+0.5LSB

DIFFERENTIAL LINEARITY ERROR

Transfer Functions for Non-Ideal 3-Bit DAC and ADC

Quantifying Data Converter Dynamic Performance

1.22

Signal-to-Noise Ratio (SNR)

Harmonic Distortion
Worst Harmonic
Total Harmonic Distortion (THD)
Total Harmonic Distortion Plus Noise (THD + N)
Signal-to-Noise-and-Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Analog Bandwidth (Full-Power, Small-Signal)
Spurious Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion (IMD)
Multi-tone Intermodulation Distortion
Noise Power Ratio (NPR)
Adjacent Channel Leakage Ratio (ACLR)
Noise Figure
Settling Time, Overvoltage Recovery Time

Sample-and-Hold Function
Required for Digitizing AC Signals
SAMPLING
CLOCK

TIMING

ANALOG
INPUT
SW
CONTROL

ADC
ENCODER
C
ENCODER CONVERTS
DURING HOLD TIME

HOLD
SW
CONTROL

SAMPLE

SAMPLE

Input Frequency Limitations of

Non-Sampling ADC (Encoder)
ANALOG INPUT
N

v(t) = q 2
2

sin (2 f t )

dv
2N
q
2 f cos (2 f t )
dt =
2
dv
dt max

= q 2(N1) 2 f
dv
dt max

fmax =

2(N1) 2 q
dv
dt max

fmax =

q 2N

N-BIT
SAR ADC ENCODER
CONVERSION TIME = 8s
fs = 100 kSPS
EXAMPLE:
dv = 1 LSB = q
dt = 8s
N = 12, 2N = 4096
fmax = 9.7 Hz

Aperture Time Aperture Delay Time

Effective Aperture Delay Time

Measured with Respect to ADC Input
+FS
ZERO CROSSING

ANALOG INPUT
SINEWAVE

0V

-FS
t e '

+t e '
SAMPLING
CLOCK
t e'

84dB

ADC

78dB

80.0

75.0

Analog
Input

72dB

50 fs

70.0

66dB
Each line shows
constant RMS
clock jitter in
femtoseconds (fs)

65.0

60dB
60.0

100 fs

Sampling Clock

200 fs

400 fs

55.0

50.0

AIN = 200 MHz

45.0
100

300
MHz

Fullscale Analog Input (sinewave)

400
MHz

500
MHz

800 fs

1000

Sampling

theory requires at least 2x over sampling

of desired signal bandwidth
SNR performance is a function of input clock jitter
and input center frequency
Trade off
SNR

over given signal bandwidth vs clock jitter vs input

frequency

27

Digital
Output
SNR

Ana
lo g

85.0

Inp

ADC

SNR of ADC @ 200 MHz

AIN varies with clock jitter

90.0

ut

Effects of Aperture Jitter and Sampling Clock Jitter

Spurious Free Dynamic Range - SFDR

DAC Settling Time

ERROR BAND

SETTLING
TIME (OUTPUT)
t=0
ERROR BAND

DEAD
TIME

SLEW
TIME

RECOVERY
TIME

SETTLING TIME (INPUT TO OUTPUT)

29

LINEAR
SETTLING

DAC Signal Construction Glitch Impulse Area

SAMPLED
SIGNAL
t
RECONSTRUCTED
SIGNAL
1
fc

IDEAL TRANSITION

TRANSITION WITH
UNIPOLAR (SKEW) GLITCH

TRANSITION WITH
DOUBLET GLITCH

t
30

DAC sin x/x Roll Off

(Amplitude Normalized)
RECONSTRUCTED
SIGNAL

t
1
fc
1
sin

3.92dB

A=

IMAGES
IMAGES

f
fc
f
fc

IMAGES
f

0
0.5fc

fc
FS FOUT

31

1.5fc
FS + FOUT

2fc
2FS FOUT

2.5fc
2FS + FOUT

3fc

LPF Required to Reject Image

Frequency

32

Analog Filter Requirements for fo = 10MHZ:

Af

= 30MSPS,
and fc = 60MSPS
ANALOG LPF

f CLOCK = 30MSPS

dB
fo

IMAGE
IMAGE

10

20

30

40

IMAGE
50

IMAGE
60

70

80

FREQUENCY (MHz)

f CLOCK = 60MSPS
dB
fo

ANALOG
LPF
IMAGE

IMAGE
33

10

20

30

40

50

60

70

80

The World Leader in High Performance Signal Processing Solutions

Analog to Digital Converters

Architectures

Analog Devices Confidential 2008 Version 1a

ADC Architectures, Applications, Resolution, Sampling Rates

24

INDUSTRIAL
MEASUREMENT

22

RESOLUTION (BITS)

VOICEBAND,
AUDIO

20

DATA ACQUISITION
VIDEO, IF SAMPLING,
SOFTWARE RADIO, ETC.

18
16

SAR
14
12

CURRENT
STATE-OF-THE-ART
(APPROXIMATE)

10
8
1.35

Precision : 10MSPS
High Speed: > 10MSPS

10

100

1k

10k

PIPELINE

100k

1M

SAMPLING RATE (Hz)

10M

100M

1G

The Comparator: A 1-Bit ADC

LATCH
ENABLE

+
DIFFERENTIAL
ANALOG INPUT

LOGIC
OUTPUT

COMPARATOR
OUTPUT

"1"

VHYSTERESIS
"0"
0
DIFFERENTIAL ANALOG INPUT
37

Basic Successive Approximation ADC

CONVERT
START
TIMING
ANALOG
INPUT

COMPARATOR
SHA

DAC

CONTROL
LOGIC:
SUCCESSIVE
APPROXIMATION
REGISTER
(SAR)

OUTPUT
1.38

EOC,
DRDY,
OR BUSY

Successive Approximation ADC Algorithm

Analogy Using Binary Weights
TEST

TOTALS:
1.39

ASSUME X = 45

IS X 32 ?

YES RETAIN 32

IS X (32 +16) ?

NO REJECT 16

IS X (32 +8) ?

YES RETAIN 8

IS X (32 +8 + 4) ?

YES RETAIN 4

IS X (32 +8 + 4 + 2) ?

NO REJECT 2

IS X (32 +8 + 4 + 2 + 1) ?

YES RETAIN 1

X = 32 + 8 + 4 + 1 = 4510

1011012

4-Bit Switched Capacitor ADC

S1

+
_
C

C/2
S3

Vin

Vref

1.41

C/4
S4

C/8
S5

S2
Sample Mode

C/8
S6

S7

Comparator

4-Bit Switched Capacitor ADC

S1

-Vin
C

Vin

_
C/2
C/4 C/8
C/8
Comparator
S3
S4
S5
S6
S7

S2
Hold Mode

Vref

S1

0V
C

Vin
Vref
1.42

+
_

C/2 C/4 C/8

C/8
Comparator
S3
S4
S5
S6
S7

S2
Redistribution Mode

AD7626 16-Bit -10MSPS

16 steps required for one
Conversion
160MHz internal frequency
6.25ns each step.

Driving the AD7944 18b 1.33MSPS

First-Order Sigma-Delta ADC

CLOCK
Kfs

INTEGRATOR

VIN

+VREF

1-BIT
DAC

LATCHED
COMPARATOR
(1-BIT ADC)

1-BIT DATA
STREAM
VREF

SIGMA-DELTA MODULATOR

fs
DIGITAL
FILTER
AND
DECIMATOR

N-BITS

fs

1-BIT,
Kfs

CK
t

Vref

VB
Vin
t

-Vref
VA
t

2.44

Oversampling, Digital Filtering,

Noise Shaping, and Decimation

A
fs

QUANTIZATION
NOISE = q / 12
q = 1 LSB

Nyquist
Operation

ADC

Kfs
ADC

Kfs

MOD

2.45

Oversampling
+ Digital Filter
+ Decimation

fs
2
fs

DIGITAL FILTER

DIGITAL
DEC
FILTER
Oversampling
+ Noise Shaping
+ Digital Filter
+ Decimation

fs

REMOVED NOISE
fs
2

Kfs
2

fs

DIGITAL
DEC
FILTER

Kfs

REMOVED NOISE
fs
2

Kfs
2

Kfs

Noise Shaping
Q

(1/F)(X-Y)
+
X

+
-

Vin
+

- Y

X-Y

Analog Filter
H(f)=1/f

1
(X Y) Q
f

YX

- Y
1-Bit
DAC

CK
+
-

Digital
Filter

1
f
Q
f 1
f 1

Multi-Bit Sigma-Delta ADC

CLOCK
Kfs

INTEGRATOR

VIN

n-BIT
Flash ADC

fs
DIGITAL
FILTER
AND
DECIMATOR

B
n-BIT
DAC

n-BIT,
Kfs

n-BIT DATA
STREAM

SIGMA-DELTA MODULATOR
47

N-BITS

fs

AD719x Application Example

Weigh Scale Loadcell or Pressure Sensor Measurement
+5V

2 mV/V
Sensitivity

IN+
OUT+

OUT-

IN-

Exceptional

precision for low speed & high speed Weigh Scale applications

8.5 nV rms noise (Gain = 128, 4.7 Hz Output Update Rate)

16 bits of noise free resolution (Gain =128, 2.4 kHz Output Update Rate)

Lowest

Offset Drift @ 5 nV/C

Power Save Mode via programmable Bridge Power Down Switch (BPDSW)
48

3-Bit All-Parallel (Flash) Converter

STROBE
+

ANALOG
INPUT
+VREF

1.5R

A KEY BUILDING BLOCK

FOR PIPELINED ADCs

R

0.5R

1.49

PRIORITY
ENCODER
AND LATCH

DIGITAL
OUTPUT

6-Bit Two-Stage Subranging ADC

ANALOG
INPUT

_
SAMPLE
AND HOLD

N1-BIT
(3-BIT)
SADC

N1-BIT
(3-BIT)
SDAC

RESIDUE
SIGNAL
N2-BIT
(3-BIT)
G
SADC

SAMPLING
CLOCK
CONTROL

OUTPUT REGISTER

N1 MSBs (3)
DATA OUTPUT,

N2 LSBs (3)
N-BITS = N1 + N2 = 3 + 3 = 6

See: R. Staffin and R. Lohman, "Signal Amplitude Quantizer,"

U.S. Patent 2,869,079, Filed December 19, 1956, Issued January 13, 1959

1.50

Residue Waveforms at Input of N2 SADC

R = RANGE
OF N2 SADC

(A) IDEAL N1 SADC

MISSING CODES
X
R
Y
(B) NON LINEAR N1 SADC
51

MISSING CODES

Generalized Pipeline Stages in a Subranging ADC

with Error Correction
(A)
+
T/H

SADC
N1 BITS

SDAC
N1 BITS

+
T/H,
1

+
SADC
N2 BITS

SDAC
N2 BITS

TO ERROR CORRECTING LOGIC

(B)
+
T/H

1.53

SADC
N1 BITS

S MDAC
N1 BITS

+
T/H

TO ERROR CORRECTING LOGIC

SADC
N2 BITS

S MDAC
N2 BITS

T/H,
2

ADC Output Configurations

PARALLEL

SERIAL LVDS
N

ADC

DCO
FCLK

Fdata

ADC

Fs

Parallel CMOS
F

data

max = 150 MSPS

data

54

Fdata max = 840Mbps?

Serial LVDS

Fs

serial CML
F max = data packet
s
length + overhead

max = Fdata * # of data

lanes / ADC resolution

On chip PLL required

Higher-end FPGA
typically required
Pins = # of data lanes
plus Frame CLK and
Data CLK

Fdata = 3.125Gbps+
Encoded

Fs

max = 420 MSPS

Interface available in
lower cost FPGAs
Pins = ADC resolution
plus DCO
High pin count

PLL

Fs

DDR LVDS
F

Fdata

Fdata

ADC

PLL

DCO

SerDes

On chip PLL required

High-end FPGA
required

Clock

recovery

Slower customer
adoption rate
2 pins

TRX System Architectures

Todays

Solution

with JESD204A
Serial Interface

solution
Tight timing
requirements

Large # of I/Os

Relaxed
Timing requirements

Minimum # of I/Os
Serdes?

32 wires

2 to 4

CPRI/
OBSAI

SERDES
chip

Dual 16B DAC

To
Antenna 1

16 wires

CPRI/
OBSAI

Serial pairs

Dual16B DAC
To
Antenna 1

1
14B ADC
Serial pair

FPGA

14B ADC

FPGA

32 wires

2 to 4
Dual 16B DAC

Serial pairs

To
Antenna 2

18 wires

Dual 16B DAC

To
Antenna 2

1
14B ADC
Serial pair

FPGA
55

FPGA

14B ADC

IF Sampling and IF Synthesis

IF Sampling Rx

CLOCK GEN/DIST

IF Synthesis Tx
POWER MANAGEMENT
& SUPERVISORY

56

The World Leader in High Performance Signal Processing Solutions

Digital to Analog Converters

Architectures

Analog Devices Confidential 2008 Version 1a

1-Bit DAC:
Changeover Switch (SPDT)
VREF
OUTPUT

64

Sampled Data System: Sampling and

Quantization

Sampled Data System: Sampling and

Quantization

Sigma-Delta DAC
N-Bits @ fs

N-Bits @ K fs

Digital
Interpolation
Filter

Analog Signal
2 Levels

1-Bit @ K fs

Digital

Modulator

1-Bit
DAC

Analog Output

Analog
Output
Filter

Single Bit

N-Bits @ fs

N-Bits @ K fs

Digital
Interpolation
Filter

Analog Signal
2M Levels

M-Bits @ K fs

Digital

Modulator
Multi Bit

1-Bit
DAC

Analog Output

Analog
Output
Filter

Simplest Voltage Output Thermometer DAC:

The Kelvin Divider ( AKA - "String DAC")
VREF
R
R
R

TO
SWITCHES

R
R
R
R

68

3-TO-8
DECODER

3-BIT
DIGITAL
INPUT

ANALOG
OUTPUT

Digital Potentiometer

Terminal A
R

3-TO-8
DECODER

TO
SWITCHES

3-BIT
DIGITAL
INPUT

TAP
R
R
R
R
Terminal B
69

The Simplest Current Output

Thermometer (Fully-Decoded) DAC
VREF
R

3-TO-7
DECODER
7

3-BIT
DIGITAL
INPUT
70

TO
SWITCHES

CURRENT
OUTPUT INTO
VIRTUAL
GROUND
(USUALLY AN
OP-AMP I-V
CONVERTER)

Voltage-Mode Binary Weighted Resistor DAC

V
OUT

R/8

R/4

LSB
VREF

71

R/2

MSB

Current-Mode R-2R Ladder Network

Resistor-Based DAC
VREF

<< R

2R

2R
MSB

2R

2R

2R

LSB
CURRENT
OUTPUT
INTO
VIRTUAL
GROUND

* GAIN TRIM IF REQUIRED

72

Segmented Voltage Output DACs

(A)
VREF

KELVIN-VARLEY DIVIDER
("STRING DAC")
A

(B)
A

VREF

KELVIN DIVIDER AND

R-2R LADDER NETWORK
OUTPUT

B
A
B

OUTPUT
A
B

NOTE:
MSB OF R-2R LADDER
ON RIGHT

B
A

73

IF THE R-2R LADDER NETWORK

IS MONOTONIC, THE
WHOLE DAC IS
MONOTONIC

Oversampling Interpolating Txdac

Simplified Block Diagram
N

fc

74

LATCH

PLL

DIGITAL
N
INTERPOLATION
FILTER

Kf c

N
LATCH

DAC

LPF

TYPICAL APPLICATION: f c = 160MSPS

f o = 50MHz
K=2
Image Frequency = 320 50 = 270MHz

fo

Multiplying DAC
Vref
Analog Output

MDAC
Digital Input
Analog Output = Vref x Digital Input x K
VREF

<< R
2R

2R
MSB

2R

2R

2R
LSB
CURRENT
OUTPUT
INTO
VIRTUAL
GROUND

* GAIN TRIM IF REQUIRED

75

The World Leader in High Performance Signal Processing Solutions

ADCs State of the Art

SAR Converters

Analog Devices Confidential 2008 Version 1a

The Need For Speed

16-bit PulSAR ADCs
Technology Leadership:
10
9

Speed MSPS

8
7

Meeting

customer need for faster

sampling rate
No compromise on performance,
keeping power to a minimum

1 MSPS

2 MSPS
0.25um

AD7622

0.25um

AD7625

AD7621

AD7677

2002
77

3 MSPS

0.6um

2
1

AD7626

0.25um

0.25um

6 MSPS

10 MSPS

2005
Year of Release

2008

2010

AD7626 and AD7625

16-Bit, 10MSPS and 6MSPS PulSAR Differential ADCs

Features
Fast Throughput, High Performance
10 MSPS (AD7626)
6 MSPS (AD7625)
SAR architecture
16-bit resolution with no missing codes
SNR: 92 dB Typ, 90dB Min @ 1MHz
INL: 1 LSB Typ, 2 LSB Max
DNL: 0.3 LSB Typ, 1 LSB Max
Differential input range: 4.096V
No latency/no pipeline delay
Serial LVDS interface
On-Board 4.096V Reference
Power dissipation 130 mW @ 10 MSPS,
100 mW @ 6 MSPS

78

Resolution
16-Bit
Input
4.096
Channels
1
INL, Max
2LSB
Interface
Serial-LVDS
Package
32-lead LFCSP

AD7980- 1MSPS, 7mW 16 Bit ADC

in MSOP/QFN

The World Lowest Power 16-Bit ADC

Lowest Power: 7mW @ 1MSPS

Power scales linearly with sampling rate
like 70W @ 10kSPS

The World Smallest Package in > 0.2MSPS 16-Bit ADC

LFSCP/QFN (SOT23 size) or MSOP

Pin-Pin compatible with AD768x

The World fastest MSOP/QFN 16-Bit ADC

Outstanding DC and AC Performance

16-Bit No Missing Code

+/-1.5LSB INL Max
20bit effective resolution @ 10kSPS

EE Times China
EE Times China
converterWinner
Winner
converter

Ease of use

2.5V main supply

0 to REF input (up to 5V) - lower cost opamp 5V/3.3V/2.5V serial SPI
Multiple ADC Daisy Chain, Busy Indicator

For
ForData
Dataacquisition,
acquisition,ATE,
ATE,Smart
SmartSensors
Sensors
and
andPortable
PortableMedical
Medicalequipments
equipments

3mm

AD7982 PulSAR ADC: 18-Bit, 1MSPS, 7mW

The World Lowest Power 18-Bit ADC

7mW @ 1MSPS
(30x lower than competition)
Power scales linearly with sampling rate:
70W @ 10kSPS

The World Smallest Package 18-Bit ADC

LFSCP/QFN (SOT23 size) or MSOP

(5x smaller than competition)
Pin-pin compatible with AD769x

Outstanding DC and AC Performance

18-bits NMC, +/-2LSB INL max

22.7 bit effective resolution @ 1kSPS

Ease of use

Easy design for ANY input ranges

0 to REF input (up to 5V) - lower cost opamp 5V/3.3V/2.5V serial SPI
Multiple ADC daisy chain, busy indicator

Released

AD7986

High Speed 2MSPS 18-bit ADC, Low Power 15mW, 4.096V

Reference, 20L-LFCSP

High Performance
Maintains

leadership position:
Smallest, Fastest, Lowest Power

Features
Lowest

power:

AD7986

15mW@ 2MSPS w/o reference

26mW@ 2MSPS w/reference

18-bit, 2MSPS

Throughput:

2MSPS
Turbo= HIGH
1.5MSPS Turbo= LOW
1.8V/2.5V/2.7V serial SPI
SNR 97dB w/external VREF
Pin for pin with AD7985 (16b), AD7944 (14b)

Resolution

Input

Channels

INL, Max

Interface

Package

18-bits

DIFF +/-VREF

1LSB typ
2.5LSB max

SPI

QFN-20

AD7609 : 18 Bit, 8-Channel Simultaneous Sampling ADC

Multi-Market Building Block for High Dynamic Range Applications simultaneous sampling

Energy

Motor Control

Features

8 channels simultaneous sampling

200KSPS for all 8 Channels
Single 5V supply operation
Differential Analog Inputs +/-20V & +/-10V
40V Differential Analog Input Range
Sensors with differential output can
connect directly to the AD7609
Analog Inputs can withstand 7KV HBM ESD
+/-16.5V Analog input clamp protection
1Meg Resistor input impedance
2nd Order Analog Anti-Alias Filter
Backend Digital filter
2.5V reference and reference buffer
SPI and Parallel interface.
64 lead LQFP Package

Performance

18 Bits No Missing Codes

INL +/- 2.5LSB (Typ)
91 dB SNR @ 200k
105 dB DR @3.125ksps (digital filter on, OSR = 64)
100mW Power (Typ)
NFS/PFS Code 0.1% FSR over Temperature

Process Control

Instrumentation

The World Leader in High Performance Signal Processing Solutions

ADCs State of the Art

Precision Sigma-Delta (-)

Analog Devices Confidential 2008 Version 1a

Precision - ADCs Most Recent

Low Power / Highly integrated
with PGA
16-/24-bit 6-ch PGA + ref
+ exc currents

AD7794/95

16-/24-bit 3-ch PGA

400-500 uA
max
4 Hz 470Hz
Temp
Pressure
Weighscale

AD7798/99

16-/20-/24-bit 3-ch PGA + ref

16/24-bit single ch
+ exc currents

AD7792/85/93

AD7796/97

Ultralow Power / Small Package

16-/24-bit 1-ch PGA

AD7788/89

16-/24-bit 1-ch PGA

AD7790/91

Highest Precision + PGA

8.5 nV Noise; 4.8 kHz
2/4-Channel

AD7190
16-bit pk-pk @
2.4kHz; G=128
Pin Programmable
15 nV Noise; 120 Hz
2/4-Channel

AD7191
130 uA max
9.5 Hz to 120 Hz
Gas Detectors
Portable

AD7170/71

Tiny Pkg
12/16-bit ADCs

AD7192

5.6 mA-7.35 mA max

4 Hz 4.8 kHz
PLC
Weighscale

4/8-Channel

AD7193
8/16-Channel

AD7190 Performance
With AC Excitation
25mm2 CSP pkg

AD7194

AD7195

16-/24-bit 2-ch PGA

AD7787

AD7767/67-1/67-2

Ease-of-Use
24/20-bit; 380 A

11 nV Noise; 4.8 kHz

2/4-Channel

WideBandwidth DC & AC

128/64/32kHz
8mW, 115dB, 18-Bit INL

AD7780/81 Bridge Sensor ADCs

Released

500 uA max
10 Hz/ 16.7 Hz
Weighscales
Pressure
Portable

AD7766/66-1/66-2
128/64/32kHz
8mW, 115dB, 16-Bit INL

AD7764
312kHz, 115dB,
Diff Amp& Ref Buffer

AD7765
156kHz, 115dB,
Diff Amp& Ref Buffer
Flexible Decimation

High Dynamic Range

24-Bit DAQ
Vibration
Medical (EEG)

AD7760/2/3
2.5MHz/625kHz
100dB,
Diff Amp & Ref Buffer
Programmable filter

AD7785/92/93/94/95 Product Description

Low Power, Highly Integrated - ADC for Temperature Sensing

Low Power 400 A typical

Low Noise 40 nV rms
Programmable Integrated Features for
Temperature Sensing
(RTDs, Thermocouples, Thermistors)

Superior offset & gain drift specs

Instrumentation Amplifier (binary gains 1 to 128)

Excitation Current Sources (10 / 210 / 1000 A)
Voltage Reference, Clock
Input Buffer, Temp Sensor
Offset = 10 nV/C; Gain = 1 ppm/C

Simultaneous 50 & 60 Hz Rejection

4 Hz to 470 Hz Output Data Rate
Supply: 2.7 V to 5.25 V
Temp: -40C to +105C

+125C option for AD7794

AD7792/85/93
16-/20-/24-bit

- ADC
3 Differential Channels
16-TSSOP Package

AD7795/94
16-/24-bit

- ADC
6 Differential Channels
24-TSSOP Package

Temperature Measurement
RTD Sensor
G N D

VD D

AD 7793

IO U T 1

BA N D G A P
R E F IN (+ )
R EFER EN C E

V D D
R L1
RTD

R E F IN (-)

G N D
A IN 1

R L2

M U X

S I G M A D E L TA
A D C

IN -A M P

S E R IA L
IN T E R FA C E
A N D
C O N TRO L
L O G IC

S P I S E R IA L
IN T E R FA C E

IO U T 2
R L3

G N D

R R EF

R E F IN

E X C I TA T I O N
C U R R EN TS

IN T E R N A L
C LO C K

C LK

KEY APPLICATION BENEFITS

3-wire RTD
2 matched excitation currents
40 nV RMS @ Gain = 64
Ratiometric Configuration
50 & 60 Hz Rejection (-70 dB)

IO V D D

Temperature Measurement
Thermocouple Sensor
G N D

VD D

A D 7793

V B IA S

V D D

BA N D G A P
R E F IN (+ )
R EFER EN C E

THERMOCOUPLE
R
JUNCTION

G N D

A IN 1

R
C

IO U T 1

S I G M A D E L TA
A D C

IN -A M P

M U X

A IN 2
G N D
R R EF

R E F IN

R E F IN (-)

E X C I TA T I O N
C U RR EN TS

S E R IA L
IN T E R FA C E
A N D
C O N TRO L
L O G IC

IN T E R N A L
C LO C K

S P I S E R IA L
IN T E R FA C E

IO V D D

C LK

KEY APPLICATION BENEFITS

Thermocouple
Internal Reference
40 nV RMS @ Gain = 64, 4 Hz Update Rate
Differential Analog Input
On-chip VBIAS Centers the Sensor Range
50 & 60 Hz Rejection

KEY APPLICATION BENEFITS

Cold Junction
Second Channel
In-Amp (Gain 1-64)
Excitation Currents
Ratiometric Measurement

Flow Measurement
Flow Sensor
VDD

REFIN1(+)

IN +

O U T-

VDD

AD7794

VDD

O UT+

O U T-

IN +

GND

AIN1
IN -

O U T+

AIN2

SIGMA DELTA
ADC

IN-AMP

MUX

REFIN1(-)

IN -

IOUT1
AIN3
T H E M IS T O R
R

REF

GND

REFIN2(+)

EXCITATION
CURRENTS

REFIN2(-)
PWRSW

INTERNAL
CLOCK

GND
CLK

KEY APPLICATION BENEFITS

Flow Sensor
Several channels required
40 nV RMS Noise (In-Amp Gain = 64)
REFIN up to AVDD
Ratiometric Configuration
50 & 60 Hz Rejection (-70 dB)

SERIAL
INTERFACE
AND
CONTROL
LOGIC

SPI SERIAL
INTERFACE

IOVDD

Pressure Measurement
Weigh Scale (Bridge Sensor / Loadcell)
+5V

G N D
R E F IN ( + )
2 m V /V
S e n s it iv it y

IN +

IN -

R EFER EN CE
DETECT

A D 7799

VDD

A IN 1 ( + )
O UT+

O U T-

A VD D

10 m V m ax

A IN 1 ( - )
A IN 2

IN - A M P

M U X

S IG M A
D ELTA A D C

A IN 3 /P 1 /P 2
R E F IN (-)

G ND

S E R IA L
IN T E R F A C E
A N D
CO NTR O L
L O G IC

IN T E R N A L
C LO C K

PW R SW

KEY APPLICATION BENEFITS

27 nV noise (In-Amp Gain = 128, 4 Hz Update Rate)
REFIN up to AVDD
Ratiometric Configuration
Medium/High Range Weigh Scales (1 count in 112, 000 (10 mV Input Range))
50 & 60Hz Rejection (-70 dB)

D O U T /R D Y
D IN
SC LK
C S

D VD D

AD7190 Product Description

2/4 Channel 4.8 kHz Ultralow Noise 24-Bit - ADC with PGA

8.5 nV rms Noise

20.5

Gain = 128, Output Data Rate = 4.7 Hz

22.5

bits noise free resolution

Gain = 1, Output Data Rate = 4.7 Hz

16

bits noise free resolution

bits noise free resolution

Gain = 128, Output Data Rate = 2.4 kHz

Output Data Rates up to 4.8 kHz

PGA: Gains from 1 to 128
INL 15ppm max (1ppm typ G=1)
Offset Drift 5 nV/C
Gain Drift 1 ppm/C
Specified Drift Over Time
AVdd = 5V; DVdd = 3V / 5V

90

Resolution

Current

Channels

Output Data Rate

Interface

Package

Temperature

24-Bit

6 mA

2/4

4.7 Hz 4.8 kHz

SPI

24-TSSOP

-40C to +105C

AD7190 Applications
4.8 kHz Ultralow Noise 24-Bit - ADC with PGA
Scientific,

Test & Commercial Instruments

Weigh

Scales (Retail, Laboratory,

Industrial Hopper & Conveyer Scales)
Chromatography for Chemical Analysis
Data Acquisition / Analyzers
Dataloggers
Industrial

Automation

PLC/DCS

Analog
Input Module Front-Ends
Temperature Controllers
Pressure Measurement
Medical
Patient

Instrumentation

Monitoring
Blood Pressure Measurement,
Temperature Measurement, Blood Analysis

91

AD719x Application Example

Weigh Scale Loadcell or Pressure Sensor Measurement
+5V

2 mV/V
Sensitivity

IN+
OUT+

OUT-

IN-

Exceptional

precision for low speed & high speed Weigh Scale applications

8.5 nV rms noise (Gain = 128, 4.7 Hz Output Update Rate)

16 bits of noise free resolution (Gain =128, 2.4 kHz Output Update Rate)

Lowest

Offset Drift @ 5 nV/C

Power Save Mode via programmable Bridge Power Down Switch (BPDSW)
92

AD7760 24 Bit, 2.5MSPS Sigma Delta ADC

KEY BENEFITS

High SNR allows accurate digitization

112dB at 78kHz, 100dB at 2.5 MHz
Reduced anti aliasing filtering
(Sigma/Delta)

Flexibility

Filter Programmability allows application

customization

Comprehensive Solution

On Chip Buffer/Amplifiers simplify

design - no need for user to select
expensive external components

AD7760 Filter Response

Resolution

Speed

Interface

Power
Supply

Package

24-Bit

2.5 MHz

Parallel

5V , 2.5V

64-TQFP_EP

AD7762
625

kSPS Version
Parallel Interface

AD7763
625

kSPS Throughput
Serial Interface
93

The World Leader in High Performance Signal Processing Solutions

ADCs State of the Art

Pipelined Converters

Analog Devices Confidential 2008 Version 1a

DPD />100MHz

ADI : New High Speed ADC Products

AD9467

20-60MHz

75MHz

16 bit 250MSPS

95

Highest Ain Performance

AD9650

AD9648 fam.

AD9253 fam.

Dual 16 bit 105MSPS

Dual 14b 125MSPS

100mW/ch Par LVDS

Quad/Octal 14b
125MSPS 100mW/ch
Par LVDS

Highest SNR (375mW/Ch)

Newly released

Sampling

AD9434 12-Bit, 370/500 MSPS, 1.8 V ADC

KEY SPECIFICATIONS

A/C Performance at 500Msps

SNR = 65.2 dBFS @ Ain up to 250 MHz
ENOB of 10.5 @ fIN up to 250 MHz
SFDR = 75 dBc @ fIN up to 250 MHz

Key Benefit
Lower Power and High Sample Rate
Pin Compatible with AD9230: 12-bit 250Msps

LVDS SDR at 500 MSPS (ANSI-644 levels)

1.2 GHz full power analog bandwidth
On-chip reference, no external decoupling
required

AD9434

Programmable via SPI

Integrated input buffer and S/H

Programmable input voltage range:
1.18 V to 1.6 V, 1.5 V nominal

Low power dissipation

660 mW @ 500 MSPLVDS SDR mode

Single 1.8 V supply operation

SPI Port for configuration and control

Selectable output data format (offset binary, twos

complement, Gray code)
Power down
Output Test patterns
Output timing adjustments

Package

Price @ 1k

56-lead LFCSP

AD9434-500: $125
AD9434-370: $90

Sampling

Final Release

Now

March2011

AD9484 8-Bit, 500 MSPS, 1.8 V ADC

KEY SPECIFICATIONS

A/C Performance at 500Msps

SNR = 47 dBFS @ Ain up to 250 MHz
ENOB of 7.5 @ fIN up to 250 MHz
SFDR = 83 dBc @ fIN up to 250 MHz

Key Benefit
Lower Power and High Sample Rate
Pin Compatible with AD9230: 12-bit 250Msps

LVDS SDR at 500 MSPS (ANSI-644 levels)

1.2 GHz full power analog bandwidth
On-chip reference, no external decoupling
required

Programmable via SPI

Integrated input buffer and S/H

Programmable input voltage range:
1.18 V to 1.6 V, 1.5 V nominal

Low power dissipation

670 mW @ 500 MSPLVDS SDR mode

Single 1.8 V supply operation

SPI Port for configuration and control

Selectable output data format (offset binary, twos

complement, Gray code)
Power down
Output Test patterns
Output timing adjustments

Package

Price @ 1k

56-lead LFCSP

AD9484-500: $36

Sampling

Final Release

Now

March2011

AD9467 16-Bit, 250 MSPS ADC

KEY BENEFITS
Outstanding Performance

Key Benefit

High effective resolution at high sampling rate.

SNR

= 75.5 dBfs @ Fin = 210 MHz @ 250 MSPS

SFDR = 90 dBFs @ Fin = 300 MHz @ 250 MSPS
SFDR = 92 dBFs @ Fin = 170 MHz @ 250MSPS
SFDR = 100dBFs @ Fin = 100MHZ @ 160MSPS
Excellent

Linearity

DNL
INL

= 0.5 LSB (16-bit Typical)

= 3.5 LSB (16-bit Typical)

LVDS DDR at 250 MSPS (ANSI-644 levels)

900 MHz Full Power Analog Bandwidth
Power Dissipation = 1.32W
2.0V p-p to 2.5 Vp-p (default) Input Voltage
Range
Integrated input buffer
External Reference supported
Data Clock Output Provided
1.8V and 3.3V supply operation
User Controls via Serial port interface

Output

Data Format Option

Clock Duty Cycle Stabilizer
Output Test patterns
Power down modes

Temp

Package

-40C +85C

72 pin 9x9mm
Pb-Free LF-CSP

Sampling

Final Release

Now

Oct 2010

The World Leader in High Performance Signal Processing Solutions

DACs State of the Art

Analog Devices Confidential 2008 Version 1a

Product-Market Focus
Core Markets

Core Products

ADI Confidential

AD5791 Product Description

1uS Update, 1ppm DAC in 0.29cm2
1ppm

Linearity

20bit

Resolution
1ppm DNL & INL
<1ppm

Noise

0.025ppm

Low freq Noise

9nVHz Wide Band Noise

1s Settling Time

to scale settling

<1ppm

Offset Drift 0.05ppm/C

Low

Drift

Glitch

0.4nVs (5v); 1nVs (10v)

Output

Spans +5V to 10V

7.5 V to 15 V Power Supply
Resolution

DNL

INL

Refresh Rate

Interface

Package

Temperature

20-Bit

1PPM

1PPM

1s

SPI

20-TSSOP

-40C to +125C

101

AD5791 Functional Block Diagram

10V 5V +10V +5V

+
-

INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC

DAC
REG

20-BIT
DAC

POWER-ON-RESET
& CLEAR LOGIC

102

10V 5V +10V +5V

Feedback & Matched Resistors

Eases Drive Amp Selection

A1

10V
5V
+10V
+5V

AD5791 Ideal for MR Imaging Applications

Exceeds All Digital-to-Analog Converter Requirements for MRI
MRI DAC Requirements:
High Resolution/Accuracy
18-20

Low

bits minimum for 3.0Tesla Systems

Noise

Lessens

unwanted image artifacts thereby

reducing the need for multiple MRI scans

Low

Drift

Eliminates

system
calibrations

Fast

Settling Time

Reduces

scan time

AD5791 Exceeds All

MRI DAC Requirements
103

Magnet
Gradient
Coil
RF Coil

HV

HV Gradient Coil
Supply Control 20-Bits
Digital
Control

AD5791
1ppm DAC

Amp
-HV

Amp
Patient

ADC

AD5422 Current Source & Voltage Out DAC

16 Bit, 4-20mA , 10V

Single Channel Configuration for Isolated

PLC Systems
16-Bit Resolution
IOUT
4mA-20mA, 0mA-20mA or 0mA-24mA
0.01% FSR TUE
4ppm/oC Output Drift
VOUT
0-5V, 0-10V, 5V, 10V
10% over-range
0.01% FSR TUE
3ppm/oC Output Drift
Force & Sense capability
Functionality
Internal 5V 10ppm/oC Reference
Diagnostics/Fault detection
Output Loop compliant AVDD-2.5V
Resolution

Features

Temp Range

16-Bit

Fault
-40oC to +85oC
Detection
www.analog.com

Related Products
AD5412
12 Bit Version
Similar Functionality

Interface
Serial

Power Supply
12V to 48V or
12V to 24V

Package
24 TSSOP
40 - LFCSP

Sensor i/ps : Thermocouple, RTD, Loadcell, Pt100, Gas, Flow etc

Measures
climate,
gas, light
intensity,
Flow rate,
temp etc.

XTAL

Sensor

Sensor

Sensor

Sensor

Mux

ADuM

LCD Display

AD779x
AD719x ADC

Standard 4 to 20mA
Communication
or bipolar Voltage Output

ADuM

DSP

Vout to
DACAD5422
4-20mA
Circuitry
Reference

www.analog.com

AD5755 Quad 16 bit V/I DAC with Dynamic

Power Control

16-Bit Quad Industrial V/I

Output DAC with Thermal Control
IOUT Range:
4-20mA, 0-20mA or 0-24mA
0.06% TUE Accuracy
5ppm/oC Output Drift
VOUT Range:
0-5V, 0-10V, 5V, 10V
20% Over-range.
0.04% TUE
Vsense + & Vsens Functionality
Flexible Digital Interface
On-chip Diagnostics
Integrated per channel DC-DC for
Dynamic Power Control
Internal 5ppm/oC Reference
Housed in 64 LFCSP (9 x 9mm)

Related Products
AD5735

Sampling , Release Spring 2011

12 Bit Version
Similar
Functionality

AD5755-1

16bit version
HART Compliant
Vsense +

AD5755 Block Diagram

Precision

16-bit DAC
DAC

Leverages ADI
Core Technologies

Smart and
and High-

Efficiency
Efficiency Dynamic
Power Control
Control (DPC)
(DPC)

Precision
Precision

Linear
Linear Signal
Signal
Processing
Processing

4 X Output

(V/4-20mA)
Channels

Diagnostics
Diagnostics

I/P
107

No Calibration Required (Full Channel Spec)

O/P

AD5764 15V 16-Bit Accurate Quad DAC

- Bipolar Cores

KEY BENEFITS

Small: 32 lead TQFP

Full 16 Bit Accuracy
1

LSB DNL
1 LSB INL(C-Grade)
2/4 LSB INL (B/A-Grade)

Ease of Application
On

chip reference buffers

Bipolar output generated from single 5V Ref

Output control during power on/off

Output

clamped to 0V during power on/off

Resolution

Output

Channels

INL, Max

Interface

Package

Status

16 Bits

10.5V

1 LSB

SPI

32-TQFP

Released

Related Products
AD5764R

Same Functionality
16 bit, Quad
Internal 10ppm Reference.

www.analog.com

AD5744/44R

Same Functionality
14 Bit, Quad
44 R Int 10ppm Ref

AD5762R

Same Functionality
16 bit, Dual
Internal 10ppm Reference

AD5541A/2A 16-Bit 1LSB, 1s, DAC

Upgrade to AD5541/42
KEY FEATURES

16-Bit 1LSB INL & DNL

Low Noise 12nV/rtHz
3V and 5V Operation
V
DD = 2.7V to 5.5V
Fast Settling @ 1s
Low Glitch: 1.1nV-sec
VLOGIC Pin with 1.8V operation
Gain Error TC: 0.1ppm/C
Zero-Code Error TC: 0.05ppm/C
Bipolar Zero TC: 0.2ppm/C (AD5542)

Related Products
AD5512A

50MHz SPI compatible Interface

Increased Interface Flexibility
Resolution
16-Bit

Feature

Temp range

1s Settling

-40oC to +125oC

ADI Confidential

Interface
Serial

12 bit
Similar Functionality
Feedback resistors
for bipolar outputs

Power Supply
2.7V to 5.5V

AD5551/52

Similar Functionality
14 bit version
8 & 14 ld SOIC

Package
8 & 10 LFCSP (41)
10 MSSOP (41)
10 &16 LFCSP (42)
16 TSSOP (42)

AD5664R 16-Bit Quad nanoDACTM in 3x3

LFCSP package
KEY BENEFITS

High Performance
16-Bit

Resolution, 12LSB INL

10-MSOP / 3x3 10-LFCSP
.and also includes an on-chip 5ppm/C Reference
70% Space saving over competition

Ideal for base-stations, optical transceivers

Reference

and non reference options

Dual Configuration also available
A Member of the nanoDAC family
Resolution

Output

Channels

INL, Max

Interface

Package

16-Bits

0-5 V

12 LSB

SPI

10-LFCSP/MSOP

AD5644R/24R

AD5663R/43R/23R

Same as AD5664R except

14/12-Bits Resolution

Same as AD5664 except

16/14/12 Bits
Dual Configuration

ADI Confidential

AD5664/24 & AD5663

Same as AD5664R except

No on-chip reference
Quad and Dual configuration

AD5291/2 256/1024 Tap, 30V or 15V,

1% R-Tol, 20-TP Wiper Memory digiPOT+
KEY FEATURES
Single-Channel,

256/1024 Tap resolution

20 k, 50 k and 100 k Nominal
Resistance
Calibrated 1% Nominal Resistor Tolerance
+4.5V to +30V Single-Supply Operation
4.5V to 15V Dual-Supply Operation
20-TP 20-Time Programmable Memory

Applications
Mechanical

potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current
conversion
Programmable filters, delays, time
constants
Programmable power supply
Sensor calibration

Temp

Price @ 1K

-40C to 105C

AD5291: $2.29
AD5292: $2.62

High Speed DAC Category Overview

Signal
Image

MixMode

Sample Rate, Integration, Performance

RF DAC

112

Frequency (GHz)

Up to 2.5GSPS
w/ Interpolation
& NCO + MixModeTM

FDAC

Frequency (GHz)

FDAC

TxDAC+ : IF Class
Signal Processing DACs
Up to 1.25GSPS
w/ Interpolation & NCO

Frequency (GHz)

FDAC

IF

TxDAC
Low Power
Base Band DAC
8-16b ; Up to 500MSPS

Frequency (GHz)

0.5
FDAC

1.0

1.5

2.0

2.5

3.0

Released

Higher
Bandwidth

Baseband-Class TxDAC
High Performance / Low Power Transmit DACs
Dual

Dual

AD9747/46/45/43/41

AD9783/81/80

16-8b, 250 MSPS

CMOS Inputs
72p QFN (10x10)

16-12b, 500 MSPS

LVDS Inputs
72p QFN (10x10)

Single
AD9707/06/05/04

AD9117/16/15/14
14-8b, 125 MSPS
CMOS Inputs
40p QFN (6x6)

Low Power

Small Footprint

Dual

14-8b, 175 MSPS

CMOS Inputs
32p QFN (5x5)
2mA output current

Dual
AD9717/16/15/14
14-8b, 125 MSPS
CMOS Inputs
40p QFN (6x6)
2mA output current

Not Preferred
Preferred

IF-Class Signal Processing TxDAC+

Quad DAC

Dual DAC

CMOS Interface

LVDS Interface

AD9788/87/85

AD9122

16-12b, 800MSPS
Interpolation + Fine NCO
100p QFP (16x16)

16b, 1.25 GSPS

Interpolation + Fine NCO
72p QFN (10x10)

AD9125
16b, 1.0 GSPS
Interpolation + Fine NCO
72p QFN (10x10)

AD9146
16b, 1.25 GSPS
Interpolation + No NCO
48p QFN (7x7)

AD9148
16b, 1.0 GSPS
Interpolation + Fine NCO
196b BGA (12x12)

Not Preferred
Preferred

RF-Class TxDAC & TxDAC+

High Performance MixMode DACs
1st Generation

2nd Generation
Single
AD9739
14b, 2.5 GSPS

Single
AD9736/35/34
14-10b, 1.2 GSPS
2x Interpolation

All LVDS Inputs

Single
AD9789
14b, 2.4 GSPS
Highly Integrated

Not Preferred
Preferred

MxFE Roadmap
Integrated Mixed-Signal Front-End
Tx
Part

Rx

Resolutio
n

Fs

Package

Resolutio
n

Fs

AD9860

10b

128
MSPS

10b

64 MSPS

128p LQFP (16 x 22)

AD9861

10b

200
MSPS

10b

50 / 80
MSPS

64p LFCSP (9 x 9)

AD9862

14b

128
MSPS

12b

64 MSPS

128p LQFP (16 x 22)

AD9863

12b

200
MSPS

12b

50 MSPS

64p LFCSP (9 x 9)

AD9963/61

130
12b/10b
1st Generation
MSPS

AD9863/2/1/0

12b/10b
2nd

100 MSPS
72p LFCSP (10 x 10)
Generation

AD9963/61
Low Power

Cosimo Carriero
Senior Field Applications Engineer
cosimo.carriero@analog.com
Mobile: +39.334.6533599