Microcontroller Intel 8051

[Instruction Set]

Structure of Assembly Language

[ label: ]

mnemonic [operands] [ ;comment ]

Example:
MOV

R1, #25H ; load data 25H into R1

8051 Assembly Language

Registers

MOV Instruction:
MOV

destination, source

Example:
1.MOV A, $55H
2.MOV R0, A
3.MOV A, R3
3

Instruction Groups
The 8051 has 255 instructions
Every 8-bit opcode from 00 to FF is used except for
A5.
The instructions are grouped into 5 groups
Arithmetic
Logic
Data Transfer
Boolean
Branching

Arithmetic Instructions
ADD
8-bit addition between the accumulator (A) and a second
operand.
The result is always in the accumulator.
The CY flag is set/reset appropriately.
ADDC
8-bit addition between the accumulator, a second
operand and the previous value of the CY flag.
Useful for 16-bit addition in two steps.
The CY flag is set/reset appropriately.

Arithmetic Instructions

DA
Decimal adjust the accumulator.
Format the accumulator into a proper 2 digit packed BCD number.
Operates only on the accumulator.
Works only after the ADD instruction.

SUBB
Subtract with Borrow.
Subtract an operand and the previous value of the borrow (carry)
flag from the accumulator.
A A - <operand> - CY.
The result is always saved in the accumulator.
The CY flag is set/reset appropriately.

Arithmetic Instructions

INC
Increment the operand by one.
The operand can be a register, a direct address, an indirect
address, the data pointer.

DEC
Decrement the operand by one.
The operand can be a register, a direct address, an indirect
address.

MUL AB / DIV AB
Multiply A by B and place result in A:B.
Divide A by B and place result in A:B.

Logical Operations

ANL / ORL
Work on byte sized operands or the CY flag.
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ANL C, bit
ANL C, /bit

Logical Operations
XRL
Works on bytes only.

CPL / CLR
Complement / Clear.
Work on the accumulator or a bit.
CLR P1.2

Logical Operations
RL / RLC / RR / RRC
Rotate the accumulator.
RL and RR without the carry
RLC and RRC rotate through the carry.
SWAP A
Swap the upper and lower nibbles of the accumulator.
No compare instruction.
Built into conditional branching instructions.

Data Transfer Instructions

MOV
8-bit data transfer for internal RAM and the SFR.
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data

Data Transfer Operations

MOV
1-bit data transfer involving the CY flag
MOV C, bit
MOV bit, C

MOV
16-bit data transfer involving the DPTR
MOV DPTR, #data

Data Transfer Instructions

MOVC
Move Code Byte
Load the accumulator with a byte from program
memory.
Must use indexed addressing
MOVC
MOVC

A, @A+DPTR
A, @A+PC

Data Transfer Instructions

MOVX
Data transfer between the accumulator and a
byte from external data memory.

MOVX
MOVX
MOVX
MOVX

A, @Ri
A, @DPTR
@Ri, A
@DPTR, A

Data Transfer Instructions

PUSH / POP
Push and Pop a data byte onto the stack.
The data byte is identified by a direct address
from the internal RAM locations.
PUSH
POP

DPL
40H

Data Transfer Instructions

XCH
Exchange accumulator and a byte variable
XCH A, Rn
XCH A, direct
XCH A, @Ri

XCHD
Exchange lower digit of accumulator with the lower digit of the
memory location specified.
XCHD A, @Ri
The lower 4-bits of the accumulator are exchanged with the
lower 4-bits of the internal memory location identified
indirectly by the index register.
The upper 4-bits of each are not modified.

Boolean Operations
This group of instructions is associated with the single-bit
operations of the 8051.
This group allows manipulating the individual bits of bit
addressable registers and memory locations as well as
the CY flag.
The P, OV, and AC flags cannot be directly altered.
This group includes:
Set, clear, and, or complement, move.
Conditional jumps.

Boolean Operations

CLR
Clear a bit or the CY flag.
CLR P1.1
CLR C

SETB
Set a bit or the CY flag.
SETB A.2
SETB C

CPL
Complement a bit or the CY flag.
CPL 40H
; Complement bit 40 of the bit
addressable memory

Boolean Operations

ORL / ANL
OR / AND a bit with the CY flag.
ORL C, 20H
; OR bit 20 of bit addressable
; memory with the CY flag
ANL C, /34H ; AND complement of bit 34 of bit
addressable memory with the CY
flag.
MOV
Data transfer between a bit and the CY flag.
MOV C, 3FH
; Copy the CY flag to bit 3F of the
bit addressable memory.
MOV P1.2, C ; Copy the CY flag to bit 2 of P1.

Boolean Operations
JC / JNC
Jump to a relative address if CY is set / cleared.
JB / JNB
Jump to a relative address if a bit is set / cleared.
JB ACC.2, <label>
JBC
Jump to a relative address if a bit is set and clear the bit.

Branching Instructions
The 8051 provides four different types of
unconditional jump instructions:
Short Jump SJMP
Uses an 8-bit signed offset relative to the 1st byte of the next
instruction.

Long Jump LJMP

Uses a 16-bit address.
3 byte instruction capable of referencing any location in the
entire 64K of program memory.

Branching Instructions
Absolute Jump AJMP
Uses an 11-bit address.
2 byte instruction
The upper 3-bits of the address combine with the 5-bit
opcode to form the 1st byte and the lower 8-bits of the
address form the 2nd byte.
The 11-bit address is substituted for the lower 11-bits of the
PC to calculate the 16-bit address of the target.
The location referenced must be within the 2K Byte
memory page containing the AJMP instruction.
Indirect Jump JMP
JMP @A + DPTR

Branching Instructions
The 8051 provides 2 forms for the CALL instruction:
Absolute Call ACALL
Uses an 11-bit address similar to AJMP
The subroutine must be within the same 2K page.
Long Call LCALL
Uses a 16-bit address similar to LJMP
The subroutine can be anywhere.
Both forms push the 16-bit address of the next instruction
on the stack and update the stack pointer.

Branching Instructions
The 8051 provides 2 forms for the return instruction:
Return from subroutine RET
Pop the return address from the stack and continue
execution there.
Return from ISV RETI
Pop the return address from the stack.
Restore the interrupt logic to accept additional
interrupts at the same priority level as the one just
processed.
Continue execution at the address retrieved from the
stack.
The PSW is not automatically restored.

Branching Instructions
The 8051 supports 5 different conditional jump instructions.
ALL conditional jump instructions use an 8-bit signed
offset.
Jump on Zero JZ / JNZ
Jump if the A == 0 / A != 0
The check is done at the time of the instruction
execution.
Jump on Carry JC / JNC
Jump if the C flag is set / cleared.

Branching Instructions
Jump on Bit JB / JNB
Jump if the specified bit is set / cleared.
Any addressable bit can be specified.

Jump if the Bit is set then Clear the bit JBC

Jump if the specified bit is set.
Then clear the bit.

Branching Instructions
Compare and Jump if Not Equal CJNE
Compare the magnitude of the two operands and
jump if they are not equal.
The values are considered to be unsigned.
The Carry flag is set / cleared appropriately.

CJNE
CJNE
CJNE
CJNE

A, direct, rel
A, #data, rel
Rn, #data, rel
@Ri, #data, rel

Branching Instructions
Decrement and Jump if Not Zero DJNZ
Decrement the first operand by 1 and jump to the
location identified by the second operand if the
resulting value is not zero.
DJNZ
DJNZ

No Operation
NOP

Rn, rel
direct, rel

Addressing Modes

Five addressing modes are available:

Immediate
Register
Direct
Indirect
Indexed

There are three more modes:

Relative
Absolute
Long
These are used with calls, branches and jumps and are handled
automatically by the assembler.

Immediate Addressing

The data is directly specified in the instruction.

Useful for getting constants into registers.
Immediate data must be preceded with a # sign.
MOV R0, #0F0H

; Load R0 with the value F0H

The immediate value is a maximum of 8-bits.

One exception, when dealing with the DPTR register it can
be 16-bits.
MOV DPTR, #2000H ; Load the value 2000H into the
DPTR register

Register Addressing Mode

Direct access to eight registers R0 through R7.

MOV A, R0
MOV R1, A
ADD A, R1
Not all combinations are valid.
MOV
R2, R1
; Invalid

There are 4 banks of registers accessible through register

addressing.
Only one bank can be accessed at a time controllable through
bit RS0 and RS1 of the PSW.
MOV
PSW, #00011000B
Set RS0:RS1 to 11, therefore, accessing register bank 3.

Direct Addressing
Direct addressing can access any on-chip hardware register.
All on-chip memory locations and registers have 8-bit
addresses.
Can use the 8-bit address in the instruction.
MOV
A, 4H
; Amem[04H]
Or can use the register name.
MOV
A, R4
Dont get confused with Immediate mode.
No # sign.

Indirect Addressing
R0 and R1 may be used as pointer registers
where their contents indicate an address in
internal RAM where the data is to be read or
written.
MOV

R1, #40H ; Make R1 point to location 40

MOV

A, @R1

; Move the contents of 40H to A

MOV

@R0, R1

; Move contents of R1 into the

; memory location pointed to by R0.

Indirect Addressing
Can also be used for accessing external memory:
Can use R0 and R1 to point to external memory
locations 00H to FFH.
MOVX A, @R1

; Move contents of external

memory location whose address
is in R1 into A

Can also use DPTR to point to all 64k of external

memory.
MOVX A, @DPTR

Indexed Addressing
Use a register for storing a pointer to memory
and another register for storing an offset.
The effective address is the sum of the two:
EA = Pointer + Offset
MOVC A, @A+DPTR

; Move byte from memory

located at DPTR+A to A.

Program Control Instructions

Unconditional Branch
ajmp addr11
ljmp addr16
sjmp rel
jmp @A+DPTR

; absolute jump
; long jump
; short jump to relative address
; jump indirect

Conditional branch
jz, jnz rel
djnz rel
cjne rel

; short conditional jump to rel. addr

; decrement and jump if not zero
; compare and jump if not equal

Subroutine Call
acall addr11
lcall addr16
ret
reti

; absolute subroutine call

; long subroutine call
; return from subroutine call
; return from ISV

Target Address
Target address can be,
absolute: A complete physical address
addr16: 16 bit address, anywhere in the 64k
addr11: 11 bit address, anywhere within 2k page.
rel: relative (forward or backward) -128 bytes to +127 bytes
from the current code location
Target address calculation for relative jumps
PC of next instruction + rel address
For jump backwards, drop the carry
PC = 15H, SJMP 0FEH
Address is 15H + FEH = 13H
Basically jump to next instruction minus two (current
instruction)

Conditional Jumps

jz, jnz : Conditional on A=0

Checks to see if A is zero
jz jumps if A is zero and jnz jumps is A not zero
No arithmetic op need be performed (unlike 8086/8085)
djnz : dec a byte and jump if not equal to zero
djnz Rn, rel
djnz direct, rel
jnc : Conditional on carry CY flag
jc rel
jnc rel
cjne : compare and jump if not equal
cjne A, direct, rel
cjne Rn, #data, rel
cjne @Rn, #data, rel

Loop using djnz

Add 3 to A ten times
mov A, #0
; clear A
mov R2, #10 ; R2 10, can also say 0AH
AGAIN: add A, #03
; add 3 to A
djnz R2, AGAIN
; repeat until R2==0
mov R5, A
; save the result in R5

Loop within loop using djnz

mov R3, #100
loop1:
loop2:

mov R2, #10

nop
djnz R2, loop2
djnz R3, loop1

; trying for 1000 loop iterations

; no operation
; repeat loop2 until R2==0
; repeat loop1 until R3==0

Unconditional Jumps
LJMP addr16
Long jump.
Jump to a 2byte target address
3 byte instruction
SJMP rel
Jump to a relative address from PC+127 to PC-128
Jump to PC + 127 (00H 7FH)
Jump to PC 128 (80H FFH)

Call Instructions

Subroutines:
Reusable code snippets
LCALL addr16
Long call.
3 byte instruction.
Call any subroutine in entire 64k code space
PC is stored on the stack
ACALL addr11
2 byte instruction
Call any subroutine within 2k of code space
Other than this, same behavior as LCALL
Saves code ROM for devices with less than 64K ROM
RET
Return from a subroutine call, Pops PC from stack