Register Layer Modeling

Agenda

Why RAL
Features/Advantages
RAL Components
Types of Prediction
Properties of uvm_reg_field

Why RAL?

Role of a verification Engineer:

Check for controllability and

observability of

Access Path

Access policy

Reset values

Generic DUT

Configuration
registers

Status registers

Memory

The usual Process (Not the UVM way)

Protocol specific tests and

sequences

Example:
Write Transaction:
Write Command
Register Address
Data

Registers

Read Transaction:
Read Command
Register Address

UVM Env

Interface

Abstract Register Tests

and Sequences
(Independent of
Protocol)

Example:
Write in
Register0
Data

Conversion
AXI
Sequence
Items

Registers
AXI
UVC

Read from
Register0

Register Layer

Interface Layer

AXI
Int

Features/Advantages

No implementation details required

Protocol independent (Deals only with
registers)
Register sequences stay abstract and same
irrespective of interfaces (AXI, APB, AHB etc..)
Address independent

Another Example
Register Layer

Write Register0
Data yyy;

Interface Layer

AXI Transaction
Address X; Data yyy
Direction AXI_write

RAL components

Adapter: Converts register transactions to bus

transactions and vice-versa.

Predictor

Register Model: Mimic of DUT registers

Conversion

Register
sequence

Register
Model

Agent
Sequencer

Adapter

Predictor

Interface
Driver

Monitor

DUT

Adapter example
class reg2bus extends uvm_reg_adapter;
virtual function uvm_sequence_item r2b (const ref uvm_reg_bus_op rw);
write_xtn ramtr;
ramtr = write_xtn::type_id::create (ramtr, this);
ramtr.write = (rw == UVM_WRITE) ? 1 : 0;
ramtr.address = rw.address;

return ramtr;
endfunction
endclass

Reg Map Example

Class reg_block extends uvm_reg_block;
`uvm_object_utils(reg_block)
Rand reg1 R1;...
uvm_reg_map reg_map;

Function void build();

...
reg_map = create_map(
.name("reg_map"),
.base_addr('h100),
.n_bytes(8), // BUS WIDTH
.endian(UVM_LITTLE_ENDIAN), .byte_addressing(1) );
endfunction
endclass

Register Model
Register Field
Memory

Register
Map

b7 b6 b5 b4 b3 b2 b1 b0
b7
b7
b7
b7

b6
b6
b6
b6

b5
b5
b5
b5

b4
b4
b4
b4

offset

Reg/Mem/Block

0x20

RegA

0x40

RegB

0x60

Memory

b3
b3
b3
b3

b2
b2
b2
b2

Target agent Adapter Handle

Target Sequencer Handle

NOTE: Register Block Contains all the above components

b1
b1
b1
b1

b0
b0
b0
b0

Register Model Automation

IPXACT (xml)

Register Model
Generation Tool

UVM Register
Package

Predictor

Gets information from the monitor

Converts bus transaction to register
transaction using the adapter
Predictor

Addr

Bus transaction

Adapter
data

Register
Map

reg
register_transaction

Types of Prediction

Controlled in the connect phase of the

environment.
Auto Prediction

Predictor is absent. Register model is updated at

the end of frontdoor read and write operation.
Fails to update the register models for nonregister transactions

Explicit Prediction

The predictor receives bus transactions at the end

of the front door read and write cycles
Advantage: Can keep track of register changes
even for sequences other than register
sequences

Properties of uvm_reg_field
m_reset - Stores the reset value
m_mirrored Stores a copy of the DUT register
value
m_desired Stores the value that needs to be
written into the DUT register
NOTE: All the above properties are local.

Methods
reset() - resets the values of all register fields
set() - sets the desired value of a register field
(in the m_desired field)
get() - get the value of m_desired property
get_mirrored_value() - retrieves the value of
m_mirrored property
write() - writes a value to the DUT
read() - reads a DUT register

update() - Internally calls write method when

m_mirrored and m_desired are unequal.
Argument to write method is m_desired value
mirror() Only returns the value of the DUT register to
m_mirrored property
Also compares the read value against the
desired value if the check argument is
UVM_CHECK.

Connection: RAL and Sequencer

class ram_tb extends uvm_env;
//Handles for register block, adapter and
predictor
function void build_phase (uvm_phase phase);
//Create register block, adapter and predictor
endfunction
Contd...

function void connect_phase(uvm_phase

phase);
block.map.set_sequencer(path of physical
sequencer);
predictor.map = path_of_map;
Predictor.adapter = path_of_adapter;
endfunction
endclass

Backdoor and Frontdoor Access

Backdoor access:
Register model uses hdl paths which are used
by simulator database to peek and poke the
hardware signals corresponding to registers
0 simulation time

Memory Sequence Example

class ram_manual_seq extends uvm_reg_seq;
//Instantiate Register Model
task body();
reg_model.reg.write(status, 'hff, .path(UVM_FRONTDOOR),
.parent(this));
reg_model.reg.read(status, data);
endtask
endclass