ASIC Tape Out: Designers' Perspective: C-DAC All Rights Reserved C-DAC/TVM/HDG/Aug'12

C-DAC/TVM/HDG/Aug12
C-DAC All Rights Reserved
www.cdac.in
ASIC Tape Out:

Designers
Perspective
SoC Design Process
Specification
Realization
Verification
Fabrication
Testing
C-DAC/TVM/HDG/Aug12
www.cdac.in
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Know the Specifications
Functionality
Speed
Area
Power
Cost
Time to market.
C-DAC/TVM/HDG/Aug12
www.cdac.in
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Realizing the Functionality

High Level Design
RTL Design
Design Capture in C, C++,

SystemC or SystemVerilog
Verilog / VHDL
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gates
FF
FF
Schematic Design
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Realizing the Functionality

PERIPHERAL
ADC
INPUT
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clock
OUTPUT
ROM
PLL
PROCESSING
LOGIC
RAM
FLASH
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Simulation, Debugging of the RTL
Confirms the realized functionality against the

required functionality
Generation of Golden RTL
VCS, NCSIM, Modelsim
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www.cdac.in
Verifying the Functionality
Implementing the
Functionality
Mapping to Hardware logic
Primitives
Simple Gates, Flip flops, Complex gates etc.
www.cdac.in
Hard macros
Memories, PLLs, Analog/RF IPs
Where to get all these hardware logic?
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Choosing the Resources

Foundry
IP Cores :
Semiconductor fabrication plant (fab) is a factory where

Integrated circuits are manufactured
Accepts the design as GDSII and delivers the IC in die form.
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Any reusable unit of logic, cell, or chip layout design
EDA Tools
Category of software tools for designing electronic systems such

as Printed Circuit Boards and Integrated Circuits
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The Foundry Menu

Technology
Feature size of the smallest length that can be

manufactured with that particular technology
gate length)
(usually
The masks for different layer have grids of squares that are
either "on" or "off, the size of each square will be half of the
specified size.
Process
Nominal
High speed
Low power
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www.cdac.in
Choosing from Foundry

Menu
Follow your Specification
Frequency of Operation
Area
Operating voltage
Power requirement
Yield
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Seek the availability of the required Third party IPs
Cost
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Semiconductor Technology
selection
5V
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5V
VOUT2
Vt = 1V
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www.cdac.in
MOSFET Structure
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www.cdac.in
Propagation Delay of Digital

Abstraction
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www.cdac.in
Propagation Delay of Digital

Abstraction
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www.cdac.in
Impact of Technology Scaling
Speed of operation
Area of Chip
Power consumption
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Selecting the Process
Regular process
High speed process
Propagation delay will be minimum

Power consumption higher
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Low power process
Multi Vt transistors
Leakage power consumption low

Propagation delay will be high
Multi voltage transistors
Reduced dynamic power
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www.cdac.in
MOSFET as a Switch
Digital circuits : MOSFET as a switch.

VGS >= VT
: Switch is ON
VGS < VT
: Switch is OFF
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www.cdac.in
MOSFET as a Switch
MOSFET: Not an Ideal switch since RON 0
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www.cdac.in
MOSFET switch behavior
VS = 5V, VT = 1V, RON = 1K RL= 15K

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The Static Discipline
Need for Static Discipline : Ensures proper switching action

VS
VS
To Switch ON the MOSFET
M1
C-DAC/TVM/HDG/Aug12
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VIN >= VT
M2
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Increasing the Device Speed
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Reduce RL ??
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CMOS Technology
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CMOS Technology
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Process Finalizing
Reduce VT
The device wont turn off abruptly when VGS drops

below VT
High VT cells consumes less leakage power but

operates at lower speed.
C-DAC/TVM/HDG/Aug12
LOW VT CELLS
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Foundry / IP Vendor
Deliverables For Hardware
Mapping
Primitive Cell Behavioral Models (Verilog)
Primitive Cell Abstract Timing Models (.Lib)
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Describes the functionality of the Cell.

Describes the functionality, propagation delay &
power consumption of the cells.
Primitive Cell Abstract layout (LEF)
Describes the pin position for ASIC layout
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input
C-DAC/TVM/HDG/Aug12
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Need for Abstract Models
output
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Mapping to Hardware :
Synthesis
Golden Register Transfer level (RTL)
Timing libraries (.Lib)
Mapping to Foundry supported primitive cells
Design Constraints (.sdc)
Functionality to be implemented
www.cdac.in
Speed, Power, Area
Synopsys Design compiler , Cadence RTL

Compiler
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Logical DRC Constraints

Max Transitions (Max Trans)
Max Capacitance (Max Cap)
Maximum allowable slew for the gates

www.cdac.in
Maximum allowable load capacitance for the

gates
Max Fan-out
Maximum number of fan-out for a gate.
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Constraints (SDC)
Speed
Clock frequency
Power
Area
C-DAC/TVM/HDG/Aug12
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How the synthesis tool Infer

hardware
Infers the Input /Output pins

Infers the registers
Infer the combinational gates
Clock treated as Ideal clock
Splits the entire design into 4 groups
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Input
2 Register (I2C)
Register 2 Register (C2C)
Register 2 Output (C2O)
Input
2 Output (I2O)
Maps the cells according to the constraints
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C-DAC/TVM/HDG/Aug12
www.cdac.in
Synthesized Logic for 800

MHz
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Static Timing Analysis

D e la y o f F lip F lo p
C L K
800 M H z
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C
D e la y o f A N D g a t e
C L K
S e t u p t im e f o r F F
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Static Timing analysis (set-up

violation)
D e la y o f F lip F lo p
C L K
1 G H z
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D e la y o f A N D
g a te
C L K
S e tu p tim e fo r F F
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www.cdac.in
Synthesized Logic for 1 GHz
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Timing Library
Models cell delay as function of input slew

and output load
Models cell power
Switching power as function of input slew and

output load
Leakage power
C-DAC/TVM/HDG/Aug12
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Synthesis
Route
Mapped Netlist
Constraints
SDC
LEF
Mapped to a specific foundry library

www.cdac.in
Place and
Layout of the cells in Abstract form

Details of Metals and Via
Timing Library
.lib
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P&R :Floorplanning
Arranging all the modules and

macros
Objectives
Minimize area
Reduce wirelength
Maximize routability
Determine shapes of flexible
blocks
Constraints
Shape of each block
Area of each block
Pin locations for each block
Aspect ratio
C-DAC/TVM/HDG/Aug12
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www.cdac.in
Floor plan
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www.cdac.in
Hard macros and Soft

macros
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The process of arranging circuit components

on a layout surface
Inputs : Set of fixed modules, netlist
Output : Best position for each module based
on various cost functions
Cost functions include wirelength, wire
routability, performance
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www.cdac.in
Placement
Good placement
No congestion
Shorter wires
Less metal levels
Smaller delay
Lower power dissipation
C-DAC/TVM/HDG/Aug12
www.cdac.in
Good placement vs Bad

placement
Bad placement
Congestion
Longer wire lengths
More metal levels
Longer delay
Higher power dissipation
41/60
www.cdac.in
Placement
C-DAC/TVM/HDG/Aug12
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Routing
Connect the various standard cells using

wires
Objective
100% connectivity of a system

Minimize area
Minimize wirelength
www.cdac.in
Constraints
Number of routing layers

Design rules
Timing (delay)
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www.cdac.in
Global Routing vs Detailed

Routing
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www.cdac.in
Detailed routing - Encounter
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Clock Routing & Power

Routing
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Clock Tree Synthesis

Why Clock needs buffering?
www.cdac.in
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www.cdac.in
Maximum fan-out of a gate
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www.cdac.in
Clock Tree Network
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www.cdac.in
Clock Tree Routing
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www.cdac.in
Clock Skew
C-DAC/TVM/HDG/Aug12
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www.cdac.in
Synchronous Counter
FF2
FF1
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www.cdac.in
Setup Timing
CLK FF1
FF1_in
CLK FF2
Skew
FF2_in
T in_to_FF1_out + T FF1_out_to_FF2_in + T set_up_FF2 = < TCLK + TSKEW

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www.cdac.in
Hold Timing
CLK FF1
FF1_in
CLK FF2
FF2_in
T in_to_FF1_out + T FF1_out_to_FF2_in >= Thold_FF2 + TSKEW

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www.cdac.in
Setup & Hold Timing
Hold Violation is Independent of Clock Frequency
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Power Routing
Creation of power grid to ensure Power Integrity
www.cdac.in
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Final layout
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Physical Verification: Design

Rule
Check
Determines
whether the physical layout of a particular chip layout
www.cdac.in
satisfies a series of recommended parameters called Design Rules
C-DAC/TVM/HDG/Aug12
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C-DAC/TVM/HDG/Aug12
www.cdac.in
Tape out
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SemiconductorManufacturingY
ield
Percentage ratio of good dies over total dies manufactured
www.cdac.in
C-DAC/TVM/HDG/Aug12
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Appendix: Inside a Semiconductor
www.cdac.in
foundry
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Appendix: Semiconductor Technology

Nodes
10 m
1971
3 m
1975
1.5 m
1982
1 m
1985
800 nm (.80 m)
1989
600 nm (.60 m)
1994
350 nm (.35 m)
1995
250 nm (.25 m)
1998
180 nm (.18 m)
1999
130 nm (.13 m)
2000
90 nm
2002
65 nm
2006
45 nm
2008
32 nm
2010
22 nm
2012
C-DAC/TVM/HDG/Aug12
www.cdac.in
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ASIC Tape Out: Designers' Perspective: C-DAC All Rights Reserved C-DAC/TVM/HDG/Aug'12

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C-DAC All Rights Reserved

ASIC Tape Out:

SoC Design Process

C-DAC All Rights Reserved

Know the Specifications

C-DAC All Rights Reserved

Realizing the Functionality

Design Capture in C, C++,

C-DAC All Rights Reserved

Realizing the Functionality

C-DAC All Rights Reserved

Simulation, Debugging of the RTL

Confirms the realized functionality against the

Generation of Golden RTL

VCS, NCSIM, Modelsim

C-DAC All Rights Reserved

Verifying the Functionality

Simple Gates, Flip flops, Complex gates etc.

Memories, PLLs, Analog/RF IPs

Where to get all these hardware logic?

C-DAC All Rights Reserved

Choosing the Resources

Semiconductor fabrication plant (fab) is a factory where

Any reusable unit of logic, cell, or chip layout design

Category of software tools for designing electronic systems such

C-DAC All Rights Reserved

The Foundry Menu

Feature size of the smallest length that can be

C-DAC All Rights Reserved

Choosing from Foundry

Seek the availability of the required Third party IPs

C-DAC All Rights Reserved

C-DAC All Rights Reserved

C-DAC All Rights Reserved

Propagation Delay of Digital

C-DAC All Rights Reserved

Propagation Delay of Digital

C-DAC All Rights Reserved

Impact of Technology Scaling

C-DAC All Rights Reserved

Selecting the Process

Propagation delay will be minimum

Low power process

Leakage power consumption low

Multi voltage transistors

Reduced dynamic power

C-DAC All Rights Reserved

Digital circuits : MOSFET as a switch.

C-DAC All Rights Reserved

MOSFET: Not an Ideal switch since RON 0

C-DAC All Rights Reserved

MOSFET switch behavior

VS = 5V, VT = 1V, RON = 1K RL= 15K

C-DAC All Rights Reserved

The Static Discipline

Need for Static Discipline : Ensures proper switching action

To Switch ON the MOSFET

C-DAC All Rights Reserved

Increasing the Device Speed

C-DAC All Rights Reserved

C-DAC All Rights Reserved

C-DAC All Rights Reserved