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CISC
RISC
Emphasis on hardware
Emphasis on software
Includes multi-clock
complex instructions
Single-clock,
reduced instruction only
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
Register to register:
"LOAD" and "STORE"
are independent instructions
ARM LTD
Licenses ARM core designs to semiconductor partners who fabricate and sell to
their customers.
ARM
Also develop technologies to assist with the design-in of the ARM architecture
Software
M Enhanced Multiplier
9/14/15
ARM
ARM
An
It
WHY ARM?
APPLICATIONS
Consumer
It
It
FEATURES OF LPC2148
PACKAGE:
16/32-bit
package.
MEMORY:
8
SPEED:
128
operation.
ADC:
DAC:
Single
output.
TIMERS:
Watchdog
timer
RTC:
Serial Interfaces:
I2C-bus:
Serial communication:
Fast GPIO:
package.
INTERRUPTS:
Vectored
16 configurable
available.
OSCILLATOR:
On-chip
integrated
oscillator
operates
with
an
Idle mode
Power-down mode
APPLICATIONS
Industrial control
Medical systems
Access control
Point-of-sale
Communication gateway
PROCESSOR MODES
ARM
-User
-Fast Interrupt Request Mode FIQ
9/14/15
17
MODES
application program run in User Mode
9/14/15
Most
Mode
change can be by
-Software control
-External interrupts
-Exception processing
18
MODES
Modes other than user mode are called privileged
modes
9/14/15
19
MODES
exception condition
9/14/15
exception occurs
20
REGISTER BANK
REGISTERS
has 37 32 bit long registers
9/14/15
ARM
22
Un-banked r0-r7
Banked r8-r14
PC r15
9/14/15
23
UN-BANKED REGISTERS
Registers r0 to r7
9/14/15
BANKED REGISTERS
Registers r8 to r14
9/14/15
25
BANKED REGISTERS
r8
to r12
9/14/15
& r14
30 32 bit registers
9/14/15
PROGRAM COUNTER
9/14/15
PC is accessed as r15
Incremented by 4 bytes for ARM state and 2 bytes for
THUMB state
Branch instruction loads destination address into the
PC
Can also be loaded using data operation instruction
28
ARM REGISTERS
SYS/USER
CPSR
r0
r1
r2
r3
r4
r5
r6
r7
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r15(PC)
CPSR
SPSR_fiq
SVC
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_svc
r14_svc
r15(PC)
CPSR
SPSR_svc
ABT
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_abt
r14_abt
r15(PC)
CPSR
SPSR_abt
IRQ
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_irq
r14_irq
r15(PC)
CPSR
SPSR_irq
UNDEFINED
9/14/15
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15(PC)
FIQ
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_und
r14_und
r15(PC)
CPSR29
SPSR_und
CPSR holds
9/14/15
30
29
28
4321
MODE
30
FLAGS
FLAGS
9/14/15
Control bits
I(7) *when set disables IRQ interrupt
F(6) *when set disables FIQ interrupt
T(5) *on T variants
T=0 ,indicates ARM execution
T=1 ,indicates THUMB execution
32
9/14/15
FLAGS
MODE
BITS (4:0)
M(4:0)
10000
10001
10010
10011
10111
11011
11111
Mode
User
FIQ
IRQ
Superviso
r
Abort
UND
SYS
33
9/14/15
handling mode
BLOCK DIAGRAM
TYPES OF BUSES
AMBA Bus
LOCAL Bus
VPB Bus
CRYSTAL OSCILLATOR
CRYSTAL OSCILLATOR
FOSC and CCLK are the same value unless the PLL
is running and connected.
mode
oscillation
mode.
PIN CONFIGURATION
1.
2.
FUNCTION
PIN
D+
10
D-
11
XTAL1
62
XTAL2
61
RTXC1
RTXC2
VSS
6, 18,
25,42,50
VSSA
VDD
52
VDDA
VREF
63
VBAT
49
FUNCTIONALITY OF PINS
FUNCTIONALITY OF PINS
0x0000 0000
0x0000 0000
0x0000 0000
1:0
3:2
slection
P0.0
P0.1
10
Function
line
00
01
10
11
00
01
PWM3
11
5:4
P0.2
01
10
00
GPIO Port 0.2
SCL0 (I2C0)
Capture 0.0 (Timer 0)
11
Reserved
7:6
P0.3
01
10
00
GPIO Port 0.3
SDA0 (I2C0)
Match 0.0 (Timer 0)
11
EINT1
9:8
0)
11:10
P0.4
11
P0.5
11
00
01
10
AD0.6
00
GPIO Port 0.5 0
01
MISO0 (SPI0)
10
Match 0.1 (Timer 0)
AD0.7
13:12
P0.6
01
10
15:14
P0.7
01
10
11
00
GPIO Port 0.6 0
MOSI0 (SPI0)
Capture 0.2 (Timer 0)
11
Reserved[1][2]
or AD1.0[3]
00
GPIO Port 0.7
SSEL0 (SPI0)
PWM2
EINT2
17:16
19:18
P0.8
P0.9
01
10
11
00
GPIO Port 0.8
01
TXD UART1
10
PWM4
11
Reserved[1][2]
or AD1.1[3]
00
GPIO Port 0.9
RxD (UART1)
PWM6
EINT3
21:20
P0.10
10
11
orAD1.2[3]
23:22
CTS
00
01
P0.11
00
GPIO Port 0.11
01
Reserved[1][2] or
(UART1)[3]
10
Capture 1.1 (Timer 1)
11
SCL1 (I2C1)
25:24 P0.12 00
GPIO Port 0.12 0
01
Reserved[1][2] or DSR
(UART1)[3]
10 Match 1.0 (Timer 1)
11
Reserved[1][2]
or AD1.3[3]
27:26 P0.13 00 GPIO Port 0.13 0
01 Reserved[1][2] or DTR (UART1)[3]
10 Match 1.1 (Timer 1)
11 Reserved[1][2]
orAD1.4[3]
29:28 P0.14 00
GPIO Port 0.14 0
01
Reserved[1][2] or DCD (UART1)[3]
10 EINT1
11
SDA1 (I2C1)
31:30 P0.15 00 GPIO Port 0.15 0
01 Reserved[1][2] or RI
(UART1)[3]
10 EINT2
11 Reserved[1][2]
orAD1.5[3]
29:28 P0.14 00
GPIO Port 0.14 0
01
Reserved[1][2] or DCD (UART1)[3]
10 EINT1
11
SDA1 (I2C1)
31:30 P0.15 00 GPIO Port 0.15 0
01 Reserved[1][2] or RI (UART1)[3]
10 EINT2
11 Reserved[1][2]
orAD1.5[3]
1:0
P0.16
00
3:2
P0.17
5:4
P0.18
01
11
7:6
P0.19
00
GPIO Port 0.18 0
Capture 1.3 (Timer 1)
10 Match 0.2 (Timer 0)
MISO1 (SSP)
9:8
P0.20
01
11
11:10 P0.21
00
13:12 P0.22
(Timer 0)
15:14 P0.23
17:16 P0.24
00 Reserved
01 Reserved
10 Reserved
11 Reserved
19:18 P0.25
21:20 P0.26
00 Reserved
01 Reserved
10 Reserved
11 Reserved
23:22 P0.27
00 Reserved
01 Reserved
10 Reserved
11 Reserved
25:24 P0.28
0)
27:26 P0.29
29:28 P0.30
31:30 P0.31
00
GPO Port only
01 UP_LED
10 CONNECT
11 Reserved
GPIO
GPIO registers are relocated to the ARM local bus so that the
APPLICATIONS
The register will give the logic value of the pin regardless of
whether the pin is configured for input or output, or as GPIO
or an alternate digital function.
Any configuration of that pin will allow its current logic state
to be read from the IOPIN register
This value does not reflect the effect of any outside world
influence on the I/O pins.
FAST GPIO
FIOCLR:Fast
FIOMASK0.
Port
Output
Clear
register
using
GPIO
PROGRAMMING
SWITCH
#include <LPC214X.H>
void delay (unsigned int );
int main()
{
IODIR0=0X00000001;
IODIR0=0X00000000;
while(1)
{
if(IOPIN0==(IOPIN0&0XFFFFFFFE))
{
IOSET0=0X00000100;
delay(1000);
}
else
{
IOCLR0=0X00000100;
delay(1000);
}
}
}
void delay(unsigned int k)
{
unsigned int i,j;
for(i=0;i<1275;i++)
for(j=0;j<k;j++);
}
................SHIFTING BOTHSIDES.......................
#include <LPC214X.H>
void delay(unsigned int a)
{
unsigned int j,k;
for(j=0;j<a;j++)
for(k=0;k<12500;k++);
}
int main()
{
unsigned int i;
PINSEL0=0X00000000;
IODIR0=0X00000000;
while(1)
{
for(i=0;i<30;i++)
{
IOSET0=1<<i;
delay(10);
IOCLR0=1<<i;
}
for(i=30;i>0;i--)
{
IOSET0=1<<i;
delay(10);
IOCLR0=1<<i;
}
}
}
INTERRUPTS IN ARM
INTERRUPT:
An interrupt is a signal from a device
attached to a computer or from a program within the
controller that causes the main program to stop and
figure out what to do next.
that takes
interrupts
called
VECTORED
INTERRUPT
CONTROLLER.
categories namely
FIQ
Vectored IRQ
In usual,
INTERRUPT
SOURCES:
VIC REGISTERS
SERIAL COMMUNICATION
Parallel transmission:
Data is sent 8 bits (byte) at a time over 8 data lines.
A few handshaking lines may be needed. One uses a 25-pin
D-shell connector and cable(DB-25 or equivalent)
Serial transmission:
Data is sent one bit at a time over one data line. In theory and
principle one needs only two lines for data, one for the signal
and the other for ground. A few clock and handshaking lines
are needed and in many PCs a 9-pin connector is used.
Simplex
Half duplex
Full duplex
ASYNCHRONOUS DATA
Synchronous Data
UART:
UART
PIN DESCRIPTION
Type
RXD0
Input
TXD0
Output
Description
Serial Input. Serial receive data.
Serial Output. Serial transmit data.
The UART0 Divisor Latch LSB Register, along with the U0DLM
register, determines the baud rate of the UART0. similarly
DLM also
BAUDRATE CALCULATION
INTERRUPT IDENTIFICATION
REGISTER
SERIAL COMMUNICATION
PROGRAMS
void sercon(void)
{
PINSEL0=0X00000005;
U0LCR=0X83;
U0DLL=0X061;
U0LCR=0X03;
}
SERIAL INTERRUPT
#include <LPC214X.H>
void uart0(void)__irq
{
if(U0IIR==0x00000002)
{
U0THR='Y';
while(!(U0LSR&0x40));
VICIntEnClr=0x00000040;
}
}
void serial()
{
PINSEL0=0x00000005;
U0LCR=0x83;
U0DLL=97;
U0LCR=0x03;
VICIntEnable=0x00000040;
U0IER=0x00000002;
VICVectAddr0=(unsigned)uart0;
VICVectCntl0=0x00000026;
}
int mian()
{
serial();
while(1)
{
U0THR='A';
while(!(U0LSR&0x40));
}
}
LIQUID CRYSTAL
DISPLAY
16X2 LCD
Allows user to read the information from the LCD and write the
information to the LCD.
R/W=1 when reading
R/W=0, when writing
E: ENABLE
used by the LCD to latch the information from its data lines.
registers.
information
LCD COMMANDS
0x38: 2 lines and 5x7 matrix
0x01: clear display screen
0x0E: display on, cursor blinking
0x06: increment cursor(shift cursor to right)
0x80: force cursor to beginning of 1st line
0xC0: force cursor to beginning of 2nd line
LCD PROGRAM
LCD PROGRAM
#include <LPC214X.H>
#define rs 0x00010000
#define en 0x00020000
void strlcd(unsigned char *);
void lcdcmd(unsigned char y);
void lcddata(unsigned char y);
void msdelay(unsigned int k);
int main()
{
IODIR1=0X003F0000;
msdelay(100);
lcdcmd(0x28);
msdelay(100);
lcdcmd(0x0E);
msdelay(100);
lcdcmd(0x01);
msdelay(100);
lcdcmd(0x06);
msdelay(100);
lcdcmd(0x80);
msdelay(100);
lcddata('I');
msdelay(100);
lcdcmd(0xc0);
msdelay(100);
strlcd("welcome to krest");
msdelay(100);
}
IOCLR1=en;
IOCLR1=0X003F0000;
IOSET1=temp1<<18;
IOSET1|=en;
msdelay(10);
IOCLR1=en;
}
void lcddata(unsigned char y)
{
unsigned char temp,temp1;
temp=0xf0 & y;
temp1=0x0f & y;
IOCLR1=0X003F0000;
IOSET1=temp<<14;
IOSET1|=rs;
IOSET1|=en;
msdelay(10);
IOCLR1=en;
IOCLR1=0X003F0000;
IOSET1=temp1<<18;
IOSET1|=rs;
IOSET1|=en;
msdelay(10);
IOCLR1=en;
}
void msdelay(unsigned int k)
{
unsigned int i,j;
for(i=0;i<k;i++)
for(j=0;j<1275;j++);
}
ANALOG TO DIGITAL
CONVERTER
N-BIT RESOLUTION
No.of bits
no.of steps
step size(mv)
8-bits
256
19.53
10-bits
1024
4.88
12-bits
4096
1.2
16-bits
65,536
0.076
TYPES OF ADC
PARALLEL ADC
- number of output lines
SERIAL ADC
- single output line
FEATURES
Power-down mode.
DESCRIPTION
ADC0
-AD0.7:6 & AD0.4:1
ADC1
-AD1.7:0
Vref
-PIN no. 63
REGISTER DESCRIPTION
Register description
-20bit reserved
-21bit PDN (powerdown mode)
-23:22bit reserved
-26:24bits START(when the burst is zero)
-27bit EDGE (raising or falling)
-31:28bits reserved
DAC
FEATURES OF DAC
Buffered output
Power-down mode
to analog, and
a bit that
trades
off
RTC
(REAL TIME CLOCK)
FEATURES OF RTC:
Measures
clock.
Provides
RTC
The Real Time Clock (RTC) is a set of counters for measuring time
when system power is on, and optionally when it is off.
The RTC is powered by its own power supply pin, VBAT, which can be
connected to a battery or to the same 3.3 V supply used by the rest of
the device.
REGISTERS CLASSIFICATION:
The
Register Group.
The
Group.
The
Register Group.
The
Divider.
I2C
FEATURES
Master/Slave.
Arbitration
between
simultaneously
transmitting
TECHNOLOGIES
TECHNOLOGIES
Wireless Communication
IR & RF
ZIGBEE
Mobile communication
Security Access
RFID & SMART CARD
MEMS ACCELEROMETER
ZigBee Technology
WHAT IS ZIGBEE ?
ZigBee
NEED FOR
ZIGBEE
ZigBee
ZigBee
ZIGBEE
ALLIANCE
The
ZIGBEE
CHARACTERISTICS
2.4 GHz, 915 MHz for North America, and 868 MHz for Europe
ZIGBEE CHARACTERISTICS
Multiple topologies : star, peer-to-peer, mesh topologies
Low power consumption with battery life ranging from
months to years
128-bit AES encryption Provides secure connections
between devices
Addressing space of up to 64 bit IEEE address devices
Up to 65,535 nodes on a network
Optional guaranteed time slot for applications
requiring low latency
Fully reliable hand-shake protocol for transfer
reliability
Range: 10 to 100m. Typical (Up to 400m max.)
DEVICE TYPES
There are three different ZigBee device types
The ZigBee (PAN) coordinator node
The Full Function Device (FFD)
The Reduced Function Device (RFD)
ZIGBEE TOPOLOGY
STAR TOPOLOGY
PEER TO PEER
TOPOLOGY
CLUSTER TREE
TOPOLOGY
ZIGBEE ARCHITECTURE
ZigBee Application
layer
ZigBee Network
layer
802.15.4 MAC
802.15.PHY
868 /
915MHz
802.15.4
PHY
2.4 Ghz
I
E
E
E
ZigBee
ALLIANCE
PHY LAYER
The PHY
MAC LAYER
The MAC
DATA TRANSFER
Information
in packets
Each packet has a maximum size of 128 bytes,
allowing for a maximum payload of 104 bytes.
The ZigBee specification supports a maximum
data transfer rate of 250 kbps for a range of up
to 100 meters
A ZigBee network has an optimal super frame
structure with a method for time synchronization
For priority messages, a guaranteed time slot
mechanism has been incorporated . This allows
high priority messages to be sent across the
network as rapidly as possible.
DATA TRANSFER
BEACON MODE
NON-BEACON MODE
DATA TRANSFER
BEACON MODE
NON-BEACON MODE
ZIGBEE MESH
NETWORKING
TECHNOLOGY COMPARISIONS
PRESENTATION ON GSM
NETWORK
WHAT IS GSM ?
Global System for Mobile (GSM) is a second
generation cellular standard developed to cater
voice services and data delivery using digital
modulation
GSM: HISTORY
GSM IN WORLD
3%
Arab World
3%
Asia Pacific
3%
3% (INDIA)
Africa
East Central Asia
4%
37%
Europe
Russia
43%
1%
4%
India
North America
South America
GSM IN INDIA
Figures: March 2005
Aircel
4%
Reliance
3%
MTNL
Spice
2%
4%
BPL
6%
Bharti
Bharti
27%
BSNL
Hutch
IDEA
BPL
IDEA
13%
Aircel
Hutch
19%
BSNL
22%
Spice
Reliance
MTNL
GSM SERVICES
Tele-services
Bearer
or Data Services
Supplementary services
TELE SERVICES
Telecommunication services that enable voice communication
via mobile phones
Offered services
- Mobile telephony
- Emergency calling
BEARER SERVICES
Include various data services for information
transfer between GSM and other networks like
PSTN, ISDN etc at rates from 300 to 9600 bps
Short Message Service (SMS)
up to 160 character alphanumeric data
transmission to/from the mobile terminal
SUPPLEMENTARY SERVICES
Call related services :
Call Waiting- Notification of an incoming call while on the handset
Call Hold- Put a caller on hold to take another call
Call Barring- All calls, outgoing calls, or incoming calls
Call Forwarding- Calls can be sent to various numbers defined by the user
Multi Party Call Conferencing - Link multiple calls together
CLIP Caller line identification presentation
CLIR Caller line identification restriction
CUG Closed user group
PSTN
ISDN
PDN
BTS
MSC
GMSC
BTS
BSC
VLR
MS
EIR
BTS
MS
AUC
HLR
SYSTEM ARCHITECTURE
MOBILE STATION (MS)
2.
SYSTEM ARCHITECTURE
MOBILE STATION (MS)
Mobile Equipment
SYSTEM ARCHITECTURE
MOBILE STATION (MS) CONTD.
Subscriber Identity Module (SIM)
SYSTEM ARCHITECTURE
BASE STATION SUBSYSTEM (BSS)
Base Station Subsystem is composed of two parts that
communicate across the standardized Abis interface
allowing operation between components made by
different suppliers
1.
2.
SYSTEM ARCHITECTURE
BASE STATION SUBSYSTEM (BSS)
Base Transceiver Station (BTS):
Encodes,encrypts,multiplexes,modulates and
feeds the RF signals to the antenna.
Frequency hopping
Communicates with Mobile station and BSC
Consists of Transceivers (TRX) units
SYSTEM ARCHITECTURE
BASE STATION SUBSYSTEM (BSS)
Base Station Controller (BSC)
SYSTEM ARCHITECTURE
NETWORK SWITCHING SUBSYSTEM(NSS)
Mobile Switching Center (MSC)
SYSTEM ARCHITECTURE
NETWORK SWITCHING SUBSYSTEM
SYSTEM ARCHITECTURE
NETWORK SWITCHING SUBSYSTEM
GSM SPECIFICATIONS-1
RF
Spectrum
GSM 900
Mobile to BTS (uplink): 890-915 Mhz
BTS to Mobile(downlink):935-960 Mhz
Bandwidth : 2* 25 Mhz
GSM 1800
Mobile to BTS (uplink): 1710-1785 Mhz
BTS to Mobile(downlink) 1805-1880 Mhz
Bandwidth : 2* 75 Mhz
GSM SPECIFICATION-II
Carrier Separation : 200 Khz
Duplex Distance
: 45 Mhz
No. of RF carriers : 124
Access Method
: TDMA/FDMA
Modulation Method : GMSK
Modulation data rate : 270.833 Kbps
Speech
GSM OPERATION
Speech
Speech decoding
Speech coding
13 Kbps
Channel Coding
Channel decoding
22.8 Kbps
Interleaving
De-interleaving
22.8 Kbps
Burst Formatting
Burst Formatting
33.6 Kbps
Ciphering
33.6 Kbps
Modulation
De-ciphering
Radio Interface
270.83 Kbps
Demodulation
PHYSICAL CHANNEL
GSM-FRAME STRUCTURE
LOGICAL CHANNELS
TCH
(traffic)
Speech
Data
BCH
2.4 kbps
4.8 kbps
9.6 kbps
FCCH(Frequency correction)
SCH(Synchronization)
CCCH
CCH
(control)
PCH(Paging)
RACH(Random Access)
AGCH(Access Grant)
Dedicated
SDCCH(Stand Alone)
SACCH(Slow-associated)
FACCH(Fast-associated)
CALL ROUTING
Call Originating from MS
Call termination to MS
OUTGOING CALL
MS sends dialled number to
BSS
2.
BSS sends dialled number to
MSC
3,4 MSC checks VLR if MS is
allowed the requested service.If
so,MSC asks BSS to allocate
resources for call.
5
MSC routes the call to GMSC
6
GMSC routes the call to local
exchange of called user
7, 8,
9,10 Answer back(ring back) tone
is routed from called user to MS
via GMSC,MSC,BSS
1.
INCOMING
CALL
1. Calling a GSM
subscribers
2. Forwarding call to
GSMC
3. Signal Setup to HLR
4. 5. Request MSRN
from VLR
6. Forward responsible
MSC to GMSC
7. Forward Call to
current MSC
8. 9. Get current status
of MS
10.11. Paging of MS
12.13. MS answers
14.15. Security checks
16.17. Set up connection
HANDOVERS
Between 1 and 2
Inter BTS / Intra BSC
Between 1 and 3
Inter BSC/ Intra MSC
Between 1 and 4
Inter MSC
SECURITY IN GSM
On air interface, GSM uses encryption and TMSI
instead of IMSI.
SIM is provided 4-8 digit PIN to validate the
ownership of SIM
3 algorithms are specified :
- A3 algorithm for authentication
- A5 algorithm for encryption
- A8 algorithm for key generation
AUTHENTICATION IN GSM
CHARACTERISTICS OF GSM
STANDARD
Fully digital system using 900,1800 MHz frequency
band.
TDMA over radio carriers(200 KHz carrier spacing.
8 full rate or 16 half rate TDMA channels per carrier.
User/terminal authentication for fraud control.
Encryption of speech and data transmission over the
radio path.
Full international roaming capability.
Low speed data services (upto 9.6 Kb/s).
Compatibility with ISDN.
Support of Short Message Service (SMS).
GSM APPLICATIONS
Mobile telephony
GSM-R
Telemetry System
- Fleet management
- Automatic meter reading
- Toll Collection
- Remote control and fault reporting of DG sets
Value Added Services
FUTURE OF GSM
2nd Generation
GSM -9.6 Kbps (data rate)
3 Generation
WCDMA(Wide band CDMA)
SEMINAR ON GPS
G PS
S pace S egm ent
C o n tro l S e g m e n t
SPACE SEGMENT:
24
GPS space
vehicles(SVs).
Satellites orbit the
earth in 12 hrs.
6 orbital planes
inclined at 55
degrees with the
equator.
This constellation
provides 5 to 8 SVs
from any point on the
earth.
CONTROL SEGMENT:
USER SEGMENT:
USER SEGMENT:
There are two services SPS and PPS
The Standard Positioning Service
SPS-
USER SEGMENT:
CROSS CORRELATION
Anti-
C/A code
The P code
The Navigation message which is a 50 Hz
signal consisting of GPs satellite orbits . Clock
correction and other system parameters
TRIANGULATION
Position
is calculated
from distance
measurement
Mathematically we
need four satellites
but three are
sufficient by
rejecting the
ridiculous answer
MEASURING DISTANCE
Distance to a satellite is determined by
measuring how long a radio signal takes to reach
us from the satellite
Assuming the satellite and receiver clocks are
sync. The delay of the code in the receiver
multiplied by the speed of light gives us the
distance
ERROR SOURCES
95% due to hardware ,environment and
atmosphere
Intentional signal degradation
Selective
availability
Anti spoofing
SELECTIVE AVAILABITY
Two components
Dither
:
manipulation of the satellite clock freq
Epsilon:
ANTI SPOOFING
Here the P code is made un gettable by
converting it into the Y code.
This problem is over come by cross correlation
ERRORS
Satellite
Errors
errors
Atmospheric
Through
propagation errors
ERRORS
freq measurement
low freq get refracted more than high freq
thus by comparing delays of L1 and L2 errors can be
eliminated
ERRORS
Troposphere causes delays in code and carrier
But they arent freq dependent
But the errors are successfully modeled
Errors due to Multipath
Receiver noise
ERRORS
Forces
Earth
GDOP
When
angles from
the receiver to the
SVs used are
similar
Good
GDOP
When
DGPS
Errors in one position
are similar to a local
area
High performance GPS
receiver at a known
location.
Computes errors in the
satellite info
Transmit this info in
RTCM-SC 104 format to
the remote GPS
Operates
GPS receiver
DGPS
Data
Links
Land
Links
Satellite
links
DGPS
SEMINAR ON GPS
Part II
Programming Of GPS
FEATURES:
SATELLITE ACQUISITION
Jupiter
Start..SRAM
Initialized start.EEPROM
Cold Start
Frozen Start
NAVIGATION MODES
3D
Navigation
2D
Navigation
At
least 4 satellites
Computes latitude, longitude,altitude and time
Less
DGPS
Navigation
Differential
Two
serial port
One
Master
SELECTION O F MODE
NMEA ROM
Result
Protocol Default
NMEA format, 4800bps 8N1
0
0
0
Header
portion (compulsory)
Data portion (optional)
1000 0001
1111 1111
M
L M
L
Message ID
Data word count
DCL0 QRAN
Header checksum
BINARY MESSAGES
BINARY MESSAGES
I/p
BINARY MESSAGE
I/p
Here
Whether
NMEA MESSAGES
These
I/P
messages
IBIT
NMEA MESSAGES
Sample Message
$GPRMC,185203,A,1907.8900,N,07533.5546,E,0.00,121.7,221101,13.8,
E*55
$ Start
of sentence
Type of sentence
UTC
Validity
Latitude & orientation
Longitude & orientation
Speed
Heading
Date
Magnetic variation and orientation
Checksum (followed by <CR> and <LF> )
RFID
RFID:
R : Radio
F : Frequency
ID : Identification
WHAT IS RFID???
Is
Ethernet
RFID
Reader
RFID Tag
RF Antenna
Network
Workstation
RFID TAGS:
Tags
Passive Tags
Active Tags
Battery powered
Higher storage capacities (512 KB)
Longer read range (300 feet)
Typically can be re-written by RF Interrogators
Cost around 50 to 250 dollars
Control Logic
(Finite State
machine)
Rx
Demodula
tor
Tag Integrated Circuit (IC)
Memory
Cells
RFID 2005
IIT Bombay
315
Source: www.rfidprivacy.org
Read-only tags
Read/Write
RFID READERS
Reader functions:
RFID
318
RFID APPLICATIONS
Retail
Security
Access control
Counterfeiting and Theft control/prevention
Location Tracking
RFID SUMMARY:
Strengths
Advanced technology
Easy to use
High memory capacity
Small size
Weaknesses
Lack of industry and application standards
High cost per unit and high RFID system integration costs
Weak market understanding of the benefits of RFID technology
Opportunities
Could replace the bar code
End-user demand for RFID systems is increasing
Huge market potential in many businesses
Threats
SMART CARDS
TECHNOLOGY
AGENDA
Machine readable plastic cards
What are smart cards
Security mechanisms
Applications
SCOSTA experience
Indian Driving License application
Introduction
A smart card, chip card, or
integrated circuit card (ICC),
is any pocket-sized card with
embedded integrated circuits which
can process data or Memory
PLASTIC CARDS
Visual
identity application
Plain
Magnetic
Visual
form
No security of data
Electronic
Machine
memory cards
readable data
Some security (vendor specific)
SMART CARDS
Processor
Cards
or without contacts.
Cards
VCC
Reset
Clock
Reserved
GND
VPP
I/O
WHATS IN A CARD?
RFU
CL
K
RST
Vcc
GND
RFU
Vpp
I/O
TYPICAL CONFIGURATIONS
256
Dedicated terminals
Usually with a small screen,
keypad, printer, often also
have biometric devices such
as thumb print scanner.
data
COMMUNICATION MECHANISMS
INS
P1
P2
Lc
1..Lc
Le
SECURITY MECHANISMS
Password
Card
holders protection
authentication
Biometric information
Persons
identification
PASSWORD VERIFICATION
Terminal asks the user to provide a password.
Password is sent to Card for verification.
Scheme can be used to permit user
authentication.
Not
CRYPTOGRAPHIC VERIFICATION
Terminal
Terminal
Terminal
Primarily
BIOMETRIC TECHNIQUES
DATA STORAGE
Data is stored in smart cards in E2PROM
Card
MF
DF
DF
EF
DF
EF
EF
EF
EF
File types
Binary file
(unstructured)
Fixed size record file
Variable size record
file
Each
Multiple
AN EXAMPLE SCENARIO
(INSTITUTE ID CARD)
Select: P2
verification
MF
EF3 (password)
EF3 (password)
P1 (User password)
P1 (User password)
P2 (sys password)
EF4 (keys)
K1 (DOSAs key)
K2 (DOFAs key)
K3 (Registrars key)
Read: Never
Write: Password
Verification (P1)
Read: Free
Write: upon
verification by K1, K2
or K3
Read: Free
Write: Password
Verification (P1)
Se
re
EF
Sh
by
DO
Re
EF
Ca
ab
W
fo
Read: Never
Write: Once
So
pa
So
DO
m
So
AN EXAMPLE SCENARIO
(INSTITUTE ID CARD)
Library
its own
under
EF2 (Address)
EF3 (password)
EF4 (keys)
DF1 (Lib)
EF1 (Issue record)
Bk# dt issue dt retn
Bk# dt issue dt retn
Bk# dt issue dt retn
Bk# dt issue dt retn
Institu
its key
under
Modifiable: By Thus l
admin staff. Read:
develo
all
EF3: Keys
K1: Issue staff key
K2: Admin staff key
applic
indepe
rest.
Application
software runs
here
The terminal itself does not store any keys, its the two cards that
really authenticate each other. The terminal just facilitates the
process.
CURRENT STATE
DL/RC are being issued in Calcutta, Delhi on
SCOSTA cards (pilot basis)
Governments such as Jharkhand, Maharastra,
Gujarat, WB have already started the process
rolling.
Various other states will follow.
DAY 21
KIT EXPLANATION