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INTRODUCTION
Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
Modern processor is a very complex device
It contains
Many registers
Multiple arithmetic units, for both integer and floating point calculations
The ability to pipeline several consecutive instructions to speed execution
Etc.
CPU
15
4095
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Instruction codes
INSTRUCTIONS
Program
A sequence of (machine) instructions
(Machine) Instruction
A group of bits that tell the computer to perform a specific operation (a
sequence of micro-operation)
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Instruction codes
INSTRUCTION FORMAT
A computer instruction is often divided into two parts
An opcode (Operation Code) that specifies the operation for that
instruction
An address that specifies the registers and/or locations in memory to
use for that operation
Addressing
mode
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Instruction codes
ADDRESSING MODES
The address field of an instruction can represent either
Direct address: the address in memory of the data to use (the address of the
operand), or
Indirect address: the address in memory of the address in memory of the data to use
Indirect addressing
Direct addressing
22
0 ADD
457
35
300
457
1 ADD
300
1350
Operand
1350
Operand
AC
AC
Instruction codes
PROCESSOR REGISTERS
A processor has many registers to hold instructions,
addresses, data, etc
The processor has a register, the Program Counter (PC) that
holds the memory address of the next instruction to get
Since the memory in the Basic Computer only has 4096 locations, the PC
only needs 12 bits
Instruction codes
PROCESSOR REGISTERS
The significance of a general purpose register is that it can be
referred to in instructions
e.g. load AC with the contents of a specific memory location; store the
contents of AC into a specified memory location
Registers
PC
Memory
11
4096 x 16
AR
15
IR
CPU
15
15
TR
7
OUTR
DR
7
15
INPR
AC
List of BC Registers
DR
AR
AC
IR
PC
TR
INPR
OUTR
16
12
16
16
12
16
8
8
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Data Register
Holds memory operand
Address Register
Holds address for memory
Accumulator
Processor register
Instruction Register Holds instruction code
Program Counter
Holds address of instruction
Temporary Register Holds temporary data
Input Register
Holds input character
Output Register
Holds output character
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Registers
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11
Registers
Bus
7
Address
Read
AR
LD INR CLR
PC
LD INR CLR
DR
LD INR CLR
E
AC
ALU
LD INR CLR
INPR
IR
TR
LD
LD INR CLR
OUTR
LD
16-bit common bus
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Clock
12
Registers
INPR
Write
Address
ALU
AC
L I
L I
L I
DR
IR
L I
TR
PC
OUTR
AR
L I
7
LD
C
2
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Registers
Register
x
AR
PC
DR
AC
IR
TR
Memory
14
Instructions
14
12 11
Opcode
0
Address
Register-Reference Instructions
15
0
12 11
Register operation
1
Input-Output Instructions
15
1 1
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12 11
1
(OP-code = 111, I = 0)
0
(OP-code =111, I = 1)
0
I/O operation
15
Instructions
Hex Code
I=0
I=1
0xxx 8xxx
1xxx 9xxx
2xxx Axxx
3xxx Bxxx
4xxx Cxxx
5xxx
Dxxx
6xxx
Exxx
Description
AND memory word to AC
Add memory word to AC
Load AC from memory
Store content of AC into memory
Branch unconditionally
Branch and save return address
Increment and skip if zero
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
7800
7400
7200
7100
7080
7040
7020
7010
7008
7004
7002
7001
Clear AC
Clear E
Complement AC
Complement E
Circulate right AC and E
Circulate left AC and E
Increment AC
Skip next instr. if AC is positive
Skip next instr. if AC is negative
Skip next instr. if AC is zero
Skip next instr. if E is zero
Halt computer
INP
OUT
SKI
SKO
ION
IOF
F800
F400
F200
F100
F080
F040
Input character to AC
Output character from AC
Skip on input flag
Skip on output flag
Interrupt on
Interrupt off
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Instructions
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Instruction codes
CONTROL UNIT
Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations
that implement them
Control units are implemented in one of two ways
Hardwired Control
CU is made up of sequential and combinational circuits to generate the
control signals
Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals
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Other inputs
3x8
decoder
7 6543 210
D0
D7
Combinational
Control
logic
Control
signals
T15
T0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit
sequence
counter
(SC)
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Increment (INR)
Clear (CLR)
Clock
19
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC 0
Clock
T0
T1
T2
T3
T4
T0
T0
T1
T2
T3
T4
D3
CLR
SC
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INSTRUCTION CYCLE
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Instruction Cycle
T1
S2
T0
S1 Bus
S0
Memory
unit
7
Address
Read
AR
LD
PC
INR
IR
LD
5
Clock
Common bus
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Instrction Cycle
T0
IR M[AR], PC PC + 1
T1
T2
I
T3
Execute
input-output
instruction
SC 0
D'7IT3:
D'7I'T3:
D7I'T3:
D7IT3:
D7
= 0 (Memory-reference)
= 0 (register)
(indirect) = 1
T3
Execute
register-reference
instruction
SC 0
T3
AR M[AR]
= 0 (direct)
T3
Nothing
Execute
memory-reference
instruction
SC 0
T4
AR M[AR]
Nothing
Execute a register-reference instr.
Execute an input-output instr.
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Instruction Cycle
r:
rB11:
rB10:
rB9:
rB8:
rB7:
rB6:
rB5:
rB4:
rB3:
rB2:
rB1:
rB0:
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SC 0
AC 0
E0
AC AC
E E
AC shr AC, AC(15) E, E AC(0)
AC shl AC, AC(0) E, E AC(15)
AC AC + 1
if (AC(15) = 0) then (PC PC+1)
if (AC(15) = 1) then (PC PC+1)
if (AC = 0) then (PC PC+1)
if (E = 0) then (PC PC+1)
S 0 (S is a start-stop flip-flop)
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MR Instructions
AND
ADD
LDA
STA
BUN
BSA
ISZ
Operation
Decoder
D0
D1
D2
D3
D4
D5
D6
Symbolic Description
AC AC M[AR]
AC AC + M[AR], E Cout
AC M[AR]
M[AR] AC
PC AR
M[AR] PC, PC AR + 1
M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4:
D0T5:
ADD to AC
D1T4:
D1T5:
DR M[AR]
AC AC DR, SC 0
Read operand
AND with AC
DR M[AR]
AC AC + DR, E Cout, SC 0
Read operand
Add to AC and store carry in E
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20
PC = 21
BSA
135
Next instruction
AR = 135
136
Subroutine
BUN
Memory
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135
BSA
135
21
Next instruction
135
21
Subroutine
PC = 136
BUN
135
Memory
26
MR Instructions
BSA:
D5T4:
D5T5:
M[AR] PC, AR AR + 1
PC AR, SC 0
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MR Instructions
ADD
LDA
D1 T 4
DR M[AR]
D0 T 5
D1 T 5
AC AC DR
AC AC + DR
SC 0
E Cout
SC 0
BUN
BSA
STA
D2 T 4
DR M[AR]
D 3T 4
M[AR] AC
SC 0
D2 T 5
AC DR
SC 0
ISZ
D4 T 4
D5 T 4
D6 T 4
PC AR
M[AR] PC
DR M[AR]
SC 0
AR AR + 1
D5 T 5
PC AR
SC 0
D6 T 5
DR DR + 1
D6 T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0
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Serial
communication
interface
Computer
registers and
flip-flops
Receiver
interface
OUTR
FGO
AC
INPR
OUTR
FGI
FGO
IEN
Keyboard
Transmitter
interface
INPR
FGI
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-- I/O Device --
/* Input */
/* Initially FGI = 0 */
loop: If FGI = 0 goto loop
AC INPR, FGI 0
/* Output */
/* Initially FGO = 1 */
loop: If FGO = 0 goto loop
OUTR AC, FGO 0
FGI=0
FGO=1
Start Input
Start Output
FGI 0
yes
FGI=0
AC Data
yes
no
More
Character
no
END
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FGO=0
no
AC INPR
yes
OUTR AC
FGO 0
yes
More
Character
no
END
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INPUT-OUTPUT INSTRUCTIONS
D7IT3 = p
IR(i) = Bi, i = 6, , 11
INP
OUT
SKI
SKO
ION
IOF
p:
pB11:
pB10:
pB9:
pB8:
pB7:
pB6:
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SC 0
AC(0-7) INPR, FGI 0
OUTR AC(0-7), FGO 0
if(FGI = 1) then (PC PC + 1)
if(FGO = 1) then (PC PC + 1)
IEN 1
IEN 0
Clear SC
Input char. to AC
Output char. from AC
Skip on input flag
Skip on output flag
Interrupt enable on
Interrupt enable off
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PROGRAM-CONTROLLED INPUT/OUTPUT
Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
Input
LOOP,
SKI DEV
BUN LOOP
INP DEV
Output
LOOP,
LOP,
LDA
SKO
BUN
OUT
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DATA
DEV
LOP
DEV
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=0
IEN
=1
=1
=1
FGI
=0
FGO
=0
=1
Interrupt cycle
Store return address
in location 0
M[0] PC
=0
Branch to location 1
PC 1
IEN 0
R0
R1
34
BUN
1120
Main
Program
255
PC = 256
1120
Main
Program
255
256
1120
I/O
Program
1
BUN
256
BUN
1120
I/O
Program
0
BUN
M[AR] TR, PC 0
RT2:
PC PC + 1, IEN 0, R 0, SC 0
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Description
start
SC 0, IEN 0, R 0
=0(Instruction
R
Cycle)
RT0
AR PC
RT1
IR M[AR], PC PC + 1
RT2
AR IR(0~11), I IR(15)
D0...D7 Decode IR(12 ~ 14)
=1(Register or I/O)
=1 (I/O)
D7IT3
Execute
I/O
Instruction
=0 (Register)
D7IT3
Execute
RR
Instruction
D7
=1(Interrupt
Cycle)
RT0
AR 0, TR PC
RT1
M[AR] TR, PC 0
RT2
PC PC + 1, IEN 0
R 0, SC 0
=0(Memory Ref)
=1(Indir)
D7IT3
AR <- M[AR]
=0(Dir)
D7IT3
Idle
Execute MR
Instruction
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D7T4
37
Description
Microoperations
Fetch
Decode
RT0:
RT1:
RT2:
Indirect
D7IT3:
Interrupt
T0T1T2(IEN)(FGI + FGO):
RT0:
RT1:
Memory-ReferenceRT2:
AND
D0T4:
ADD
D0T5:
D1T4:
LDA
D1T5:
D2T4:
STA
D2T5:
BUN
D3T4:
BSA
D4T4:
ISZ
D5T4:
D5T5:
D6T4:
D6T5:
D6T6:
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AR PC
IR M[AR], PC PC + 1
D0, ..., D7 Decode IR(12 ~ 14),
AR IR(0 ~ 11), I IR(15)
AR M[AR]
R1
AR 0, TR PC
M[AR] TR, PC 0
PC PC + 1, IEN 0, R 0, SC 0
DR M[AR]
AC AC DR, SC 0
DR M[AR]
AC AC + DR, E Cout, SC 0
DR M[AR]
AC DR, SC 0
M[AR] AC, SC 0
PC AR, SC 0
M[AR] PC, AR AR + 1
PC AR, SC 0
DR M[AR]
DR DR + 1
M[AR] DR, if(DR=0) then (PC PC + 1),
SC 0
38
Description
Microoperations
Register-Reference
D7IT3 = r
IR(i) = Bi
r:
CLA
rB11:
CLE
rB10:
CMA
rB9:
CME
rB8:
CIR
rB7:
CIL
rB6:
INC
SPA
rB5:
SNA
rB4:
SZA
rB3:
SZE
rB2:
HLT
rB1:
rB0:
Input-Output
INP
OUT
SKI
SKO
ION
IOF
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D7IT3 = p
IR(i) = Bi
p:
pB11:
pB10:
pB9:
pB8:
pB7:
pB6:
39
40
T2
D'7
I
T3
From bus
12
12
AR
To bus
Clock
LD
INR
CLR
R
T0
D
T4
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CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN 1 (I/O Instruction)
pB6: IEN 0 (I/O Instruction)
RT2: IEN 0 (Interrupt)
p = D7IT3 (Input/Output Instruction)
D
I
T3
p
B7
B6
IEN
R
T2
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S2
Encoder
S1
S0
x1 x2 x3 x4 x5 x6 x7
0
1
0
0
0
0
0
0
For AR
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
S2 S1 S0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Multiplexer
bus select
inputs
selected
register
none
AR
PC
DR
AC
IR
TR
Memory
D4T4: PC AR
D5T5: PC AR
x1 = D4T4 + D5T5
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Design of AC Logic
16
16
8
Adder and
logic
circuit
16
16
AC
To bus
LD
INR
CLR
Clock
Control
gates
AC AC DR
AND with DR
AC AC + DR
Add with DR
AC DR
Transfer from DR
AC(0-7) INPR
Transfer from INPR
AC AC
Complement
AC shr AC, AC(15) E Shift right
AC shl AC, AC(0) E
Shift left
AC 0
Clear
AC AC + 1
Increment
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Design of AC Logic
CONTROL OF AC REGISTER
Gate structures for controlling
the LD, INR, and CLR of AC
From Adder
and Logic
D0
T5
D1
AND
D2
T5
p
B11
r
B9
DR
B7
B6
B5
ADD
16
16
AC
To bus
Clock
LD
INR
CLR
INPR
COM
SHR
SHL
INC
CLR
B11
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Design of AC Logic
AC(i)
AND
Ci
Ii
FA
C i+1
From
INPR
bit(i)
LD
ADD
DR
INPR
AC(i)
COM
SHR
AC(i+1)
SHL
AC(i-1)
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