Module I

CPU Arithmetic: Signed addition and subtractionBCD adder Multiplication Array

multiplier Booths Algorithm, Division Restoring and non-restoring division.

Computer Organization
Computer organizationrefers to
the operational units and their
interconnection that realize the
architecture specification.
It defines
how
the hardware
operates.

Computer Design
It defines the hardware structure of
the system.
It defines how the hardware is
arranged.

Computer Architecture
Computer architectureis a set of
disciplines
that
describes
acomputersystem by specifying its
parts and their relations.

DIGITAL COMPUTER
It is a digital system that performs
various computational tasks.
It use binary number system which
has only two digits ie..1 and 0.
A binary digits is called a bit.
Information is represented as a group
of bits.
A group of 8 bits is called a byte.

 A computer system is divided into 2

functional entities:
1. Hardware
2. Software

 A
hardware
consists
of
all
components and electromechanical
devices that comprise the physical
entity of a devices.
A software consists of instructions or
data that the computer manipulate
to perform various data processing
task.

Program
A sequence of instructions for the
computer to perform a task.

Data base
The memory in which data
manipulated by the program is
stored.

Operating system
It is the interface between user and
the machine.
Eg:-Windows.Linux

 Hardware part of a computer is

divided into three
1. I/O system
2. Memory
3. CPU

 CPU is again divided into 3

1. Register -Stores information
2. ALU -It performs arithmetic and logic
operations.
3. Control Unit -It controls the
functioning of the system.

CPU
Acentral processing unit(CPU)
(formerly
also
referred
to
as
acentral
processor
unit)
is
thehardwarewithin acomputerthat
carries
out
theinstructionsof
acomputer programby performing
the
basic
arithmetical,
logical,
andinput/outputoperations of the
system.

CPU

Memory
RAM
ROM

RAM
Volatile.
Data can be changed

ROM
Non volatile.
Data cannot be changed

Translator
Program that translates high level
language to machine language.
Two types:
1. Interpreter compiles line by line
2. Compiler compiles the code as a
whole.

Interrupt
Normal execution of programs may
be preempted if some device
requires urgent servicing.
The normal execution of the current
program must be interrupted the
device raises an interrupt signal.
Interrupt-service routine
After servicing the interrupt , the
execution of the current program is
again started.

Bus Structures
There are many ways to connect
different parts inside a computer
together.
A group of lines that serves as a
connecting path for several devices
is called a bus.
There are different types of buses.
Address bus
Data bus
Control bus

Address Bus

Through the address bus, processor

issues the
address of the instruction byte or
word to the
memory system.
Through the address bus, processor
execution
unit, when required, issues the
address of the data (byte or word) to
the memory system.

Data Bus

When the Processor issues the address of the

instruction, it gets back the instruction
through the data bus.
When it issues the address of the data, it
loads
the data through the data bus.
When it issues the address of the data, it
stores the data in the memory through the
data bus.

Control Bus

Issues signals to control the timing of

various actions during
interconnection.
Bus signals to synchronize the
subsystems.

SINGLE BUS
It is also called system bus.
Asystem busis a singlecomputer busthat
connects the major components of a computer
system.
The technique was developed to reduce costs and
improve modularity.
It combines the functions of a data busto carry
information, anaddress busto determine where it
should be sent, and acontrol busto determine its
operation.

 All units are connected to a single bus, so it provides the

sole means of interconnection.
Single bus structure has advantages of simplicity and low
cost.
Single bus structure has disadvantages of limited speed
since usually only two units can participate in a data
transfer at any one time. This means that an arbitration
system is required and that units will be forced to wait.
Only two units can actively use the bus at any given time.
Bus control lines are used to arbitrate multiple requests
for the use of the bus.
Buffer Registersare used to hold information during
transfers.

TWO BUS STRUCTURE

 In the first configuration, the processor is placed

between the I/O unit and the memory unit.
The processor is responsible for any data transfer
between the I/O unit and the memory unit.
The processor acts as a messenger.
In this structure, the processor performance and
capability is not being maximized.
Most of the time, the processor is doing data
transfer between these units instead of
performing more complex applications. Also, the
processor is idle most of the time waiting for
these slow devices.

 In the second configuration, I/O transfers

are made directly to or from the memory.

A special purpose processor called

peripheral processor or I/O channel is
needed as part of the I/O equipment to
control and facilitate such transfers. This
special processor is the direct memory
access(DMA) controller.
It allows main memory to perform data
transfer between I/O units.

NUMBER
REPRESENTATION

 There are three ways for

representing numbers
1. Sign & magnitude
2. 1s complement
3. 2s complement
In all the 3 systems, the left most bit
is zero for +ve numbers and 1 for
ve numbers.

Sign & Magnitude

In the sign & magnitude system, the
ve values are represented by
changing the MSB from 0 to 1.

Sign and Magnitude Representation

-7
-6
-5

1111
1110

+0
0000
+1
0001

1101

0010

+2

-4

1100

0011

+3

0 100 = + 4

-3

1011

0100

+4

1 100 = - 4

-2

1010

0101

1001

-1

0110
1000

-0

0111

+5

+6

+7

High order bit is sign: 0 = positive (or zero), 1 = negative

Three low order bits is the magnitude: 0 (000) thru 7 (111)

1s complement
In this system, -the negative
values
are
obtained
by
complementing each bit of the
corresponding +ve numbers.
1s complement of a given
number
is
equivalent
to
subtracting that number from 2n-1
ie 1111

Ones Complement Representation

-0
-1
-2

1111
1110

+0
0000
+1
0001

1101

0010

+2

-3

1100

0011

+3

0 100 = + 4

-4

1011

0100

+4

1 011 = - 4

-5

1010

0101

1001

-6

0110
1000

-7

0111

+5

+6

+7

Subtraction implemented by addition & 1's

complement

2S COMPLEMENT
It is obtained by adding 1 to the 1s
complement of that number.

Twos Complement Representation

-1
-2
-3
like 1's comp
except shifted
one position
clockwise

1111
1110

+0
0000
+1
0001

1101

0010

+2

-4

1100

0011

+3

0 100 = + 4

-5

1011

0100

+4

1 100 = - 4

-6

1010

0101

1001

-7

0110
1000

-8

0111

+7

+6

+5

Addition & Subtraction

There are two rules for adding and
subtracting 2 binary numbers using
2s complement system.
1. Addition rule
2. Subtraction rule

Addition rule
To add 2 numbers, convert the 2 +ve
numbers into binary form and omit
carry bit. If there is a ve value ,
convert it into +ve value by finding
the 2s complement & add it with the
binary form of the other number and
discard the carry.

Binary form

0
1
2
3
4
5
6
7
8

0000
0001
0010
0011
0100
0101
0110
0111
1000

 Eg: 3 + 5 =8
0 1 1+
101
-------1000

 Eg: 3 + -5
ie 3-5=-2
First find the binary of 3 ie 0011
Find the binary of -5 ie 0101 (5)
1s complement of 5 ie
1010
2s complement of 5 ie
1010+1=1011
Add 0011 (3) and 1011(-5)=1110 =-2
Binary of -2=0010=1101+1=1110

Subtraction Rule

To subtract 2 +ve numbers , convert

it into binary form, find the ones
complement of the 2nd number and
add it to the first number. In the case
of a ve number, find the 2s
complement of the ve number and
then find the 2s complement of that
number.

 Eg: -7 - -5
-701111000+11001
-501011010+11011
10110100+10101
1 0 0 1+
0101
-----------1110

 Eg: -3- -4
-300111100+11101
-401001011+11100
11000011+10100
1 1 0 1+
0100
---------0001

 The basic operation in all digital

computers is addition & subtraction.
The arithmetic operations are
implemented along with logic
function AND,OR,NOT and XOR.
The sign numbers are those numbers
which has a sign associated with it ie
for ve numbers and + for +ve
numbers.

 Here xi and yi are i/ps.si is the sum

and ci is the carry out.
Each stage of the addition must
accommodate a carry bit.
Ci represent carry in to the ith stage.
The logic expression
for si can be
implemented in a 3 i/p XOR gate.

 The component symbol of a

computer circuit for a single stage
addition is called a full adder.

ADDITION/SUBTRACTION
LOGIC

 This logic is used to perform the

subtraction operation X-Y, ie finding the 2s
complement of Y and add it to X .
It is used to perform either addition or
subtraction based on the value applied to
the add/sub input control line.
This line is set to 0 for addition, applying
the Y vector unchanged to one of the adder
inputs along with a carry-in signal,c0.

 When the add/sub control line is set

to
1,the
Y
vector
is
1s
complemented by the XOR gates and
c0 is set to 1 to complete the 2s
complementation of Y.

BINARY CODED DECIMAL

ADDER(BCD)

 BCD of a number is sum of the binary

of that number and binary
representation of six.
Up to 9, BCD and binary
representation are same.
Above 9,add binary representation of 6
to that digit in binary form.
4 bit representation of binary no: is
called BCD number.

 Eg: 131101
BCD of 13
1101+
0110
______
10011

 In BCD numbers are usually represented by

4 bits.
BCD represent the decimal range between 0
and 9.
A pair of BCD digits can be added to
generate a BCD result.
A BCD adder is a circuit that adds 2 BCD
digits in parallel and produces a sum which
is also another BCD number.

 A BCD adder must include a correction

logic in its digital construction. Its purpose
is to add 6(0110) to its sum.
For this ,a 2nd 4 digit binary adder is used.
The two decimal digits together with i/p
carry are 1st added in the top 4 bit adder
to produce the binary sum.
When the o/p carry=0,nothing is added to
the binary sum.

 When it is equal to 1,add 0110 ie 6 is

added to the binary sum through the
bottom 4 bit binary adder.
o/p carry generated from the bottom
4 bit binary adder is ignored.

WHAT IS CARRY LOOK AHEAD

ADDER ???

A carry-look ahead adder (CLA)

is a type of adder used in digital
logic to reduce carry
propagation time.

Carry-look ahead adder

x

c4

Bcell

G3

Bcell

P3

G2

P2

Bcell

G
1

G
0

Carrylookaheadlogic

4-bit carry-look ahead

adder

Bcell

P
0

Problem caused by ripple carry adder

Ripple Carry Adders take the time more to
calculate the carry alongside
the sum as well as
to propagate
the carry.

Inventors of Carry Look Ahead

Adder
Charles Babbage first lighted on the problems
caused by ripple carry adders.
Gerald Rosenberger of IBM first gave a patent of
Carry Look Ahead Adders.

Propagate & generate

Propagate P and Generate G in a CLA is given
by,
Pi=Ai
Bi
Gi=Ai Bi

Ai
Bi

Pi
Gi

Carry outputs
The Boolean expressions for carry outputs of
various stages can be written as follows :
C1=G0+P0.C0
C2=G1+G0. P1+C0. P0. P1
C3=G2+G1. P2+G0. P1. P2+C0. P0. P1. P2
C4=G3+G2. P3+G1. P2. P3+G0. P1. P2. P3+C0. P0. P1. P2. P3

Advantage of carry look ahead

adder
Like ripple carry adder we need not to wait for
the propagation of carries to get the sum.
More efficient than carry save adder.

Disadvantage of carry look ahead

adders
The disadvantage of CLA is that the carry logic block
gets very complicated for more than 4-bits.

Multiplication

Multiplication of unsigned numbers

Product of 2 n-bit numbers is at most a 2n-bit number.

Unsigned multiplication can be viewed as addition of shifted
versions of the multiplicand.

Multiplication of unsigned numbers

(contd..)
We added the partial products at end.
Alternative would be to add the partial products at
each stage.

Rules to implement multiplication are:

If the ith bit of the multiplier is 1, shift the
multiplicand and add the shifted multiplicand to the
current value of the partial product.
Hand over the partial product to the next stage
Value of the partial product at the start stage is 0.

Combinatorial array
multiplierCombinatorial array multiplier
Multiplicand
0

m3 0

m2 0

m1 0

q0
0

PP1

q2
0

PP3
q3
0
p6

p5

p4

p3

p1

p0

M
ul
tip

q1
0

PP2

p7

m0

lie
r

(PP0)

p2
,

Product is: p7,p6,..p0

Multiplicand is shifted by displacing it through an array of adders.

Multiplication of unsigned numbers

Typical multiplication cell
Bitofincomingpartialproduct(PPi)

jthmultiplicandbit
ithmultiplierbit

ithmultiplierbit

carryout

FA

carryin

Bit of outgoing partial product (PP(i+1))

Combinatorial array multiplier

Combinatorial array
multipliers are:
Extremely inefficient.
Perform only one function at one
time.

Sequential multiplication
Recall the rule for generating partial
products:
If the ith bit of the multiplier is 1, add the
appropriately shifted multiplicand to the
current partial product.
Multiplicand has been shifted left when added
to the partial product.

However, adding a left-shifted

multiplicand to an unshifted partial
product is equivalent to adding an
unshifted multiplicand to a right-

Sequential Circuit
Multiplier
RegisterA(initially0)
Shiftright
an

a0

n 1

MultiplierQ
Add/Noadd
control

n-bit
Adder

Control
sequencer

MUX

0
m

n 1

MultiplicandM

m0

 This circuit performs multiplication by using

a single n-bit adder n times to implement
the spatial addition performed by the n
rows of ripple carry adders.
Registers A and Q combined hold PPi while
multiplier bit qi generates the signal
Add/Noadd. This signal controls the
addition of the multiplicand,M,to PPi to
generate PP(i+1).
The product is computed in n cycles.

 The product grows in length by one bit per

cycle from PP0 .
The carry out from the ladder is stored in flipflop C.
At the start, the multiplier is loaded into register
Q, the multiplicand into register M and C and A
are cleared to 0.
At the end of each cycle, C , A and Q are shifted
right one bit position to allow the growth of
partial product and the multiplier is shifted out
of register Q.

 Because of this shifting , multiplier

bit qi appears at the LSB position of
Q to generate the Add/ Noadd signal
at the correct time.
After they are used , the multiplier
bits are discarded by the right-shift
operation.
The carry out from the adder is the
leftmost bit of PP(i+1) and it must be
held in C which is shifted right with

 After n cycles, the high-order half of

the product is held in register A and
the lower half is in register Q.

Sequential multiplication (contd..)

M
1101

Initialconfiguration

0000

1011

1101

1011

0110

1
0

1101

Add
Shift

Firstcycle

0011
1001

1101
1110

Add
Shift

Secondcycle

0
0

1001
0100

1110
1111

Noadd
Shift

Thirdcycle

0001

1111

1000

1111

Add
Shift

Fourthcycle

Product

Signed Multiplication

Signed Multiplication
sign extension

Signextensionis
showninblue

1
1

Signextensionofnegativemultiplicand.

Signed Multiplication
For a negative multiplier, a straightforward
solution is to form the 2s-complement of
both the multiplier and the multiplicand
and proceed as in the case of a positive
multiplier.
This is possible because complementation
of both operands does not change the
value or the sign of the product.
A technique that works equally well for
both negative and positive multipliers
Booth algorithm.

Booth Algorithm

0
1

0
1
0

0
1
0
1

0
0

1 0 1 1 0
0 +1 +1 + 1+1

1
0

0
1
0
1
1

0
0
1
1
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
1
1
0
1

0
1
0
1

0
0
1

0
1

Booth Algorithm

0 1
0 +1

0
0

1
0

1 0
0 1

1
0

0
1
0
0
0
0
0

0
1
0
0
0
0
0

0
1
0
0
0
0
0

0
1
0
0
0
1
0

0
1
0
0
0
0
0

0
1
0
0
0
1
0

0
1
0
0
0
1
0

0
0
0
0
0
0
0

0
1
0
0
0
1

0
0
0
0
0

0
0
0
0

0
1
0

0
1

2'scomplementof
themultiplicand

Booth Algorithm
In general, in the Booth scheme, -1 times the shifted
multiplicand is selected when moving from 0 to 1, and
+1 times the shifted multiplicand is selected when
moving from 1 to 0, as the multiplier is scanned from
right 0to 0left.
1
0
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0 +1 1 +1

0 1

0 +1

0 1 +1 1 + 1

Boothrecodingofamultiplier.

0 1

Booth Algorithm
Multiplier
Bit i

Bit i 1

V ersionofmultiplicand
selectedbybiti

0 XM

+ 1 XM

1 XM

0 XM

Boothmultiplierrecodingtable.

Booth Algorithm
0 1 1 0 1
X1 1 0 1 0

0 1 1 0 1
0 1 +1 1 0
0
1
0
1
0

0
1
0
1
0

0
1
0
1
0

0
1
0
0
0

0
1
1
0
0

0
0
1
1
0

0 0 0 0
0 1 1
0 1
1

1 1 1 0 1 1 0 0 1 0

Boothmultiplicationwithanegativemultiplier.

Booth Algorithm
Best case a long string of 1s (skipping over 1s)
Worst case 0s and 1s are alternating
0

Worstcase
multiplier
+1 1 +1 1 +1 1 +1 1 +1 1 +1 1 +1 1 +1 1

Ordinary
multiplier
0 1 0

0 + 1 1 +1

0 1 +1

0 1

0 +1

0 1

0 +1

0 1

Good
multiplier

Integer Division

Manual Division
13

21
274
26

1101

14
13
1

Longhanddivisionexamples.

10101
100010010
1101
10000
1101
1110
1101
1

Longhand Division Steps

Position the divisor appropriately with respect
to the dividend and performs a subtraction.
If the remainder is zero or positive, a quotient
bit of 1 is determined, the remainder is
extended by another bit of the dividend, the
divisor is repositioned, and another subtraction
is performed.
If the remainder is negative, a quotient bit of 0
is determined, the dividend is restored by
adding back the divisor, and the divisor is
repositioned for another subtraction.

Circuit Arrangement
Shiftleft
an

qn1

a0

an1

DividendQ

N+1bit
adder

q0
Quotient
Setting

Add/Subtract

Control
Sequencer
0

m0

mn1
DivisorM

Figure6.21.Circuitarrangementforbinarydivision.

Restoring Division
Shift A and Q left one binary position
Subtract M from A, and place the
answer back in A
If the sign of A is 1, set q0 to 0 and
add M back to A (restore A);
otherwise, set q0 to 1
Repeat these steps n times

Examples

1 0
1 1

10 0 0
1 1
1 0

Initially 0
0
Shift
0
Subtract 1
Set q0 1
Restore
0
Shift
0
Subtract 1
Set q0 1
Restore
0
Shift
0
Subtract 1
Set q0 0

0
0
0
1
1

0
0
0
1
1

0
1
0
0
1
1
0
1
0
1
1
1
0
0
0

0
1
1
1
0
1
1
0
1
1
1
0
0
1
1

1 0 0 0

0
0
1
1

0
0
1
1

0
0
1
0

0
1
1
0

Shift
0 0 0 1
Subtract 1 1 1 0
Set q0 1 1 1 1
Restore
1
0 0 0 1

0
1
1
1
0

0 0 0 1
0 0 1

Remainder

0 0 0
Firstcycle
0 0 0 0
0 0 0
Secondcycle
0 0 0 0
0 0 0
Thirdcycle

Fourthcycle
0 0 1 0
Quotient

Arestoringdivisionexample.

Nonrestoring Division
Avoid the need for restoring A after an
unsuccessful subtraction.
Any idea?
Step 1: (Repeat n times)
If the sign of A is 0, shift A and Q left one bit
position and subtract M from A; otherwise, shift A
and Q left and add M to A.
Now, if the sign of A is 0, set q0 to 1; otherwise,
set q0 to 0.

Step2: If the sign of A is 1, add M to A

Examples
Initially

1 1 1 1 1
0 0 0 1 1
Add 0 0 0 1 0
Remainder

Restore
remainder

Shift
Subtract
Set q 0

0
0
0
1
1

Shift
Add
Set q

0 0 0

1 1 1 0 0
0 0 0 1 1
1 1 1 1 1

0 0 0

1 1 1 1 0
0 0 0 1 1
0 0 0 0 1
0 0 0 1 0
1 1 1 0 1
1 1 1 1 1

0 0 1

Shift
Add
Set q

Shift
Subtract
Set q
0

0
0
0
1
1

0
0
0
1
1

0
1
0
0
1

0
1
1
1
0

Anonrestoringdivisionexample.

1 0 0 0
0 0 0

Firstcycle

0 0 0 0

Secondcycle

0 0 0 0

Thirdcycle
0 0 0 1

Fourthcycle
0 0 1 0
Quotient