Summer School on VLSI

Introduction to VHDL
By
Santashraya Prasad

VHDL Presentation
1.

1.

2.

Brief introduction to VHDL structure

.
Library

Entity

Architecture
Structural/Data Flow/Behavioral descriptions

What is it

Syntax

Special Cases

Data type
Test Benches

What are they

How to use

examples

VHDL
VHDL

is a acronym which stands for VHSIC

Hardware Description Language
VHSIC stands for Very High Speed
Integrated Circuits
The purpose of this programming language is
to assist circuit designers to describe the
characteristics of circuit.

Standard Libraries
Include library ieee; before entity declaration.
ieee.std_logic_1164 defines a standard for designers to use in
describing interconnection data types used in VHDL modeling.
ieee.std_logic_arith provides a set of arithmetic, conversion,
comparison functions for signed, unsigned, std_ulogic, std_logic,
std_logic_vector.
Ieee.std_logic_unsigned provides a set of unsigned arithmetic,
conversion, and comparison functions for std_logic_vector.
See all available packages at
http://www.cs.umbc.edu/portal/help/VHDL/stdpkg.html

How VHDL Looks

Each

section of VHDL code is broken down

into two parts

The entity

which describes the interface and how the component

or circuit interacts with the outside world

The architecture

which describes the function of the component or

circuit

The Entity
The entity syntax

Name of Entity
Name of Input Pins

entity latch is
port (s,r: in bit;
q, nq: out bit);
end latch;

s
r

q
Latch

nq

Name of Output pins

The Architecture
The architecture syntax

Entity name
architecture belongs
to

Description of the
architecture (what it
is)

architecture structure of latch is

begin
q<= s nor nq;
nq<= r nor q;
end structure;
s

nq

Description of circuit

Description types
VHDL

can be structured in three different

ways.

Structural
Data flow
Behavioral

Usually,

a mixture of all three methods are

used in the design of the circuit

Structural Description

Structural description uses text to show how components

of a circuit are put together

The structural method is similar to a block diagram

similar to a schematic capture approach to designing a circuit

It is to combine smaller blocks or predefined components in to a
larger circuit by describing the way that the blocks interact
smaller components are used to make a circuit without knowing
what is happening in the block

It can be thought of as a netlist

A netlist is used to describes how components are connected

together form a circuit.

Structural Syntax
Architecture description
entity latch is
describes the architecture is of
port (s,r: in bit;
the method structure description
q, nq: out bit);
and belongs to the entity latch
end latch;
architecture structure of latch is
Component Pin
component nor_gate
Specifications
port (a,b: in bit;
These are used to describe the input
and output pins of the component
c: out bit);
nor_gate that will be used in the
end component;
architecture section
begin
n1: nor_gate port map (r, nq, q);
Mapping pins to
n2: nor_gate port map (s=>a, q=>b, nq=>c);
component
The command port map is used to
end structure;

show how the input and output pins

are connected to the component
nor_gate
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Description Representation
Architecture

a
nor_gate c

a
nor_gate c

nq
Entity
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Internal Signals

It is also possible to use internal signals to the architecture

These are signals that are only used for connectivity within the
architecture.
This would be used if two components inputs and outputs are
connected together without being connected to any pin
described in the entity
They are defined between the architecture line and the begin
line
link
A

architecture structure of full_adder is

component halfadder
port (a,b: in bit;
B
carry, sum: out bit);
end component;
signal link : bit;
C
begin
...
End structure;

sum

HalfAdder
b

carry

sum

Sum

HalfAdder
b

carry

Carry

Full Adder
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Advantages of Structural
description

Hierarchy

allows for the simplification of the design

Component Reusability

allows the re-use of specific components of the

design (Latch, Flip-flops, half-adders, etc)

Design Independent
allows for replacing and testing components without
redesigning the circuit

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Data Flow

Data flow describes how the data flows through the

circuit, from input to output
It uses built in functions to describe the flow of data
All commands in Data flow are concurrent
(occur at the same time)
Data flow operates in discrete time, when changes occur
on the input, it immediately affects the output of the
circuit
This method is like the more traditional way of designing
a circuit using gates
For some traditional hardware designers, it is easier to
use the data flow method, since it deals with the
traditional method of designing circuits.

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Data Flow Syntax

Architecture description
entity latch is
port (s,r: in bit;
q, nq: out bit);
end latch;
architecture dataflow of latch is
begin
q<= s nor nq;
nq<= r nor q;
end dataflow;

s
q

describes the architecture is of

the method data flow description
and belongs to the entity latch

Logical Data Assignment

Shows that the value of the
output pins are derived from
a logical function of the
input pins
<= is used for a signal assignment,
which describes how the data on the
right hand side of the operator to the
left hand side.

nq
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Behavioral Descriptions

Unlike the other two methods for describing the

architecture, behavioral description is like a
black box approach to modeling a circuit

It is designed to do a specific task, how it does it is

irrelevant

It is used to model complex components which

are hard to model using basic design elements
Behavioral is often more powerful and allows for
easy implementation of the design
Most texts they combine both data flow and
behavioral descriptions into one

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Behavioral description

Behavioral descriptions are supported inside a process

statement
A process is used to describe complex behaviors of the
circuit
The contents of a process can include sequential
statements
These sequential statements are similar to commands
in conventional programming languages (it, for, etc)
which can only be used in the body of a process
statement
Although, inside a process is sequential, the process
itself is concurrent, all processes in a architecture begin
execution at the same time
The process statement is declared in the body of the
architecture in the same way as signal assignments in
data flow.
17

Elements of a Process

Processes can have a list of signals that they depend on,

a sensitivity list, or they can use wait signals to make the
process wait for a event to occur (not both)
They are only execute if the signals in the sensitivity list
change
This makes it critical to ensure that the signals that the
process depends on are in the sensitivity list.
Each process is executed once upon power up of the
system.
Wait statements are similar to sensitivity lists, but have
the advantage of forcing a process to wait at any point
within the process, not just the beginning.

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Process syntax of a counter

Process label
(optional)

Process is
dependent only on
variable x also
termed sensitivity
Variable is set to a value of -1
list.
count: process (x)
since the process is run once at
variable cnt : integer := -1;
startup to bring the value to 0
begin
cnt:=cnt + 1;
Increments the variable
end process
cnt every time the
signal of x changes

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Variables
Variables in VHDL behave similar to those in
conventional programming languages
They are used to represent the state of a
process and are local to that process
They are declared in a similar way to that of a
signal in data flow or structural descriptions

variable TempVar : integer := -1;

As shown above, Variables are declared before

the begin keyword of a process.

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Variables and Signals

signal x, y, z : bit;
process (y)
begin
x<=y;
z<=not x;
end process

process (y)
variable x,z : bit;
begin
x:= y;
z:= not x;
end process;

It should be realized that signals and variables are different. On the left both commands
in the process are concurrent, they occur at the same time. This results in z not being the
opposite of y but the opposite value of x when the process is begun.
Since the example on the right is using variable, which are sequential, the value of z is the
complement of y.
Signal assignment statements do not take effect immediately.
Variable assignments take effect immediately.
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Behavioral vs. Structural vs. Data

flow
Structural
How components are put together

nor
nor

Data Flow
Describes how data flows from input to output

Behavioral
Describes the behavior of the circuit
within a process

process (r,s)
begin
if (r nor nq) then
q <= 1;
else
q <= 0;
endif
...
end process
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Sequential vs Concurrent Statements

VHDL provides two different types of execution:

sequential and concurrent.
Different types of execution are useful for
modeling of real hardware.

Supports various levels of abstraction.

Sequential statements view hardware from a

programmer approach.
Concurrent statements are order-independent
and asynchronous.

Sequential Style

Data flow Style

Structural Style

Component Instantiation Syntax

The instantiation has 3 key parts

Name
Component type
Port map

Sequential Style Syntax

Assignments are executed sequentially inside

processes.

Sequential Statements

{Signal, Variable} assignments

Flow control

if <condition> then <statments>

[elsif <condition> then <statments>]
else <statements>
end if;
for <range> loop <statments> end loop;
while <condition> loop <statments> end loop;
case <condition> is
when <value> => <statements>;
when <value> => <statements>;
when others => <statements>;

Wait on <signal> until <expression> for <time>;

Data Objects

There are three types of data objects:

Signals

Can be considered as wires in a schematic.

Can have current value and future values.

Variables and Constants

Used to model the behavior of a circuit.

Used in processes, procedures and functions.

Constant Declaration

A constant can have a single value of a given type.

A constants value cannot be changed during the
simulation.
Constants declared at the start of an architecture can
be used anywhere in the architecture.
Constants declared in a process can only be used
inside the specific process.
CONSTANT constant_name : type_name [ : = value];

CONSTANT rise_fall_time : TIME : = 2 ns;

CONSTANT data_bus : INTEGER : = 16;

VHDL Data Types

Variable Declaration

Variables are used for local storage of data.

Variables are generally not available to multiple
components or processes.
All variable assignments take place immediately.
Variables are more convenient than signals for the
storage of (temporary) data.

Signal Assignment

A key difference between variables and signals is

the assignment delay.

Variable Assignment

IF vs CASE statement Syntax

FOR vs WHILE statement Syntax

For is considered to be a
combinational circuit by some
synthesis tools. Thus, it cannot have
a wait statement to be synthesized.

While is considered to be an FSM

by some synthesis tools. Thus, it
needs a wait statement to be
synthesized.

WAIT statement Syntax

The wait statement causes the suspension of a process

statement or a procedure.
wait [sensitivity_clause] [condition_clause] [timeout_clause];

Sensitivity_clause ::= on signal_name

wait

CLOCK;

Condition_clause ::= until boolean_expression

wait

on

until

Clock = 1;

Timeout_clause ::= for time_expression

wait

for

150 ns;

Sensitivity-lists vs Wait-on statement

Built-In Operators

Logic operators

Relational operators

+, -, &

Multiplication operators

=, /=, <, <=, >, >=

Addition operators

AND, OR, NAND, NOR, XOR, XNOR (XNOR in VHDL93 only!!)

*, /, mod, rem

Miscellaneous operators

**, abs, not

VHDL Test Bench

VHDL test bench is VHDL code that produces stimuli to test

your design correctness.

It can automatically verify accuracy of the VHDL code

Given a known input, does the system generate the expected

output

Verifies that the VHDL code meets the circuits specifications

Test benches should be easily modified, allowing for future use
with other code
Should be Easy to understand the behavior of the test bench

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Purpose for Test Bench

a)

To generate stimulus signals for simulation

1.

2.
3.

Generate specific stimuli based on the previous

output response
Apply a basic waveform with discrete time intervals
Import test data from files

b) To apply these stimulus to the VHDL code under

test and collect the actual output responses
c) To compare the output responses with the
values expected

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Stimulus Generation/Response
There is three general ways of generating a
simulation for testing

Repetitive patterns

1.

Patterns can generated using different frequencies and

periods
Combination of waveforms

Lookup table

2.

Constant table

I/O data

3.

(Waveform A and B)

Keyboard
Data file

Response Handling

The response from the system can be dumped to a file to

be analyzed by a external program or human eye (Textio).
Analyzed by test bench to verify expected output.
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Test Bench
Unit Under Test
Monitor Program
that generates
output
Resulting Output
File

Program that
generates Stimuli

Human Eye or
External Program

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