Sunteți pe pagina 1din 137

Multilevel inverter topologies with

reduced power circuit complexity for


medium voltage high power induction
motor drives by cascading conventional
two-level and three-level inverters
Sheron
Figarado

Centre for Electronics Design


and Technology

Overview of the presentation

Multilevel inverter topologies


Three-level Common mode voltage elimination schemes
Simulation and Experimental results
Four-level scheme with CMV elimination and capacitor
balancing
Simulation and Experimental results
Five-level inverter scheme
Simulation and Experimental results
Conclusion

Centre for Electronics Design


and Technology

Advantages of Multilevel
inverters over two-level inverter

Devices of lower rating can be used thereby


enabling the schemes to be used for high voltage
applications.
Reduced total harmonic distortion (THD).
Since the dv/dt is low, the EMI from the system is
low.
Lower switching frequencies can be used and
hence reduction in switching losses.

Centre for Electronics Design


and Technology

Disadvantages of multilevel
inverters

The number of isolated DC-links are more


compared to a two-level inverter.
Neutral point voltage variations.
Power bus structure and hence the control
schemes become complex as the number of
levels increases.
Decrease in Reliability

Centre for Electronics Design


and Technology

Conventional two-level
inverter

Two-level inverters switches between +


state (+Vdc/2) and state(-Vdc/2) with
respect to the O point.
The Inverter has 8 switching states for 7
phasor locations.

Centre for Electronics Design


and Technology

Three-level inverters- NPC

A 3-level inverter has 3 levels of


switching namely +Vdc/2 (+state),
0 and Vdc/2 (- state).
The NPC inverter has 27
switching states for 19 locations.

Centre for Electronics Design


and Technology

Three-level inverters- cascaded

Cascaded 3-level inverter has


a simpler power bus structure
and reduced device count.
It has switching states same
as NPC 3-level inverter.

Centre for Electronics Design


and Technology

Three-level inverters- open end


winding configuration

The voltage rating of the DC bus is half that of 2-level inverter.


Two isolated DC-links are required to avoid zero sequence
currents.
In this configuration we get 64 switching states for 19 vector
locations, whereas the conventional 3-level NPC inverter gives
only 27 switching states for 19 locations.
Centre for Electronics Design
and Technology

Reduced Switch Count Three-level


Space phasor generation schemes
with Common Mode Voltage
Elimination using cascaded two-level
inverters for an open- end winding
IM drive

Centre for Electronics Design


and Technology

Common mode voltage Common mode voltage is defined as


Definition
V +V +V
VCM = AO BO CO
3

where VAO ,VBO and VCO are the pole voltages

For an open end winding Common mode


voltage is defined as
VCM VCM 1 VCM 2
where VCM 1 is the common mode voltage of inverter 1 and
VCM 2 is the common mode voltage of inverter 2.

Centre for Electronics Design


and Technology

Effect of common mode


voltage

PWM inverters generate high frequency and high


amplitude common mode voltages, which induces
shaft voltages on the rotor side.
When the induced shaft voltage exceeds the
breakdown voltage of the lubricant in the bearings,
result in large bearing currents
This causes premature failure of the motor bearings
and also poses EMI issues.
In open end winding configuration, isolated DC links
are needed to avoid heavy currents due to the
common mode voltages in the phase windings.
The best solution for all these is to eliminate the CMV
itself.

Centre for Electronics Design


and Technology

CMV groups
The switching states of the inverter can be classified in terms
of the common mode voltage they generate.
Grou
p

Switching states of 3level


inverter

Common mode voltages


generated

+++

Vdc/2

++0, +0+, 0++

Vdc/3

+ +, ++ , ++, 00+, 0+0,


+00

Vdc/6

000, 0+ , 0 +, +0 , + 0,
0+, +0

+, + , +

, 00 , 00,
00,

Vdc/6

0 , 0 ,0

Vdc/3

Vdc/2

If we select only those states with same common mode


voltage then the variation in CMV will not be there.
Centre for Electronics Design
and Technology

2-level CMV elimination


scheme

We can select a 2-level


structure with zero common
mode voltage out of the 3level structure.
The common mode
eliminated structure has a 30
degree shift.

Centre for Electronics Design


and Technology

Five-level inverter scheme

This 5-level scheme needs 4 isolated DC links and 24


switches.
Inverter is fed by two three-level inverters from both
sides.
Centre for Electronics Design
and Technology

5-level scheme hexagonal


structure
There are 729 states for 61
locations compared to 125
switching states for the
conventional 5-level structure.
A 3-level structure with switching
states of same CMV can be selected
from this 5-level structure.

Centre for Electronics Design


and Technology

CMV groups for one inverter for open-end


winding configuration (CMV at the poles)
The switching states of the inverter can be classified in terms
of the common mode voltage they generate.
Group

Switching states of 3level


inverter

Number
of
multiple
states

Common
mode
voltages
generated

+++

Vdc/4

++0, +0+, 0++

Vdc/6

+ +, ++ , ++, 00+, 0+0,


+00

Vdc/12

000, 0+ , 0 +, +0 , + 0,
0+, +0

+, + , + , 00 , 00, 00

Vdc/12

0 , 0 ,0

Vdc/6

Vdc/4

Centre for Electronics Design


and Technology

CMV eliminated hexagons


Group C has CMV=+Vdc/12 in
the pole voltages.
If the inverters on both sides
uses the states from group C
CMV in the phase voltage is
eliminated.
36 switching states for 19
locations.
3 multiple switching states for
each location in the inner
hexagon.

Centre for Electronics Design


and Technology

CMV eliminated hexagons


Group D has CMV=0 in the pole
voltages.
If the inverters on both sides
uses the states from group D
CMV in the phase voltage is
eliminated.
49 switching states for 19
locations.
4 multiple switching states for
each location in the inner
hexagon.

Centre for Electronics Design


and Technology

CMV eliminated hexagons


Group E has CMV= -Vdc/12 in
the pole voltages.
If the inverters on both sides
uses the states from group E
CMV in the phase voltage is
eliminated.
36 switching states for 19
locations.
3 multiple switching states for
each location in the inner
hexagon.

Centre for Electronics Design


and Technology

3-level CMV eliminated scheme

Since there is no CMV, isolated DC links are not needed.


The scheme gives CMV elimination in all modulation range up to 6 step
mode.
The linear modulation range is reduced to 0.5Vdc compared to SVPWM
scheme where the linear range is 0.577Vdc.
Centre for Electronics Design
and Technology

Motivation for the Proposed


scheme

Even after the selective switching for the common


mode voltage elimination, the three-level
structure have higher multiplicity in the switching
states compared to the conventional NPC threelevel inverter without CMV elimination.
This suggests that some optimization is possible
in the power circuit.

Centre for Electronics Design


and Technology

States of individual switches for the group E


CMV eliminated structure
Switching
state of
Inverter I

Switching
state of
Inverter II

S11

S21

S31

S13

S23

S33

S11

S21

S31

S13

S23

S33

00

00

00

00

00

00

Centre for Electronics Design


and Technology

Configuration I with switching states of


group E

The scheme has 18 switches and needs two isolated DC links.


The inverters on either side share the top inverter.
Thus both the inverters cannot be switched independently.
Thus all the states are not possible for the second inverter
once the switching state of the other inverter is fixed.
Centre for Electronics Design
and Technology

Possible switching states of


inverter II given the switching
state of Inverter I
State of any
phase of
inverter- I

Possible states
of inverter- II

+,

0,

+,0,

Centre for Electronics Design


and Technology

Hexagonal space vector structure for


Configuration I
There is no multiplicity for the
vector locations except for zero
state.
Zero vector has a multiplicity of 3.

Centre for Electronics Design


and Technology

PWM signal generation for the


proposed three-Level inverter
with common mode voltage
A SVPWM generationelimination
algorithm is used to generate the switching
times for the phasor locations of the conventional three-level
inverter.
The PWM generation is based only on the sampled amplitude of
the reference voltages.
The algorithm has a linear relationship between output voltage
fundamental and reference input.
For generating PWM, the space phasor locations of the proposed
scheme is compared to that of a conventional three-level
structure.
To compensate for the 30 degree shift, the reference itself is preshifted by 30 degree.
Centre for Electronics Design
and Technology

Mapping from conventional 3-level


scheme to CMV eliminated 3-level
scheme
V S' V S e j 30

The mapping of these signals of conventional three-level inverter to the


proposed three-level scheme is implemented using a look- up method
implemented in CPLD.
Centre for Electronics Design
and Technology

Drive control scheme (V/f)

Centre for Electronics Design


and Technology

Simulation and
experimental results for
configuration I

Centre for Electronics Design


and Technology

Results for 20Hz(2-level operation)Configuration I

Pole voltages and phase voltage [Y axis


100V/division, X axis- 0.02s/div]

Pole voltages and phase voltage [Y


axis 50V/division, X axis- 0.01s/div]

FFT of the pole voltage waveform [X axis- order


of harmonic, Y axis- Normalized amplitude]

Centre for Electronics Design


and Technology

Results for 20Hz(2-level operation)Configuration I

Phase voltage and phase current [Y axisvoltage 50V/div, current 1A/div, X axis
0.05/div]

Phase voltage and phase current [Y axis


voltage 100V/div, current 1A/div, Y axis0.02s/div]

FFT of the phase voltage waveform [X axisorder of harmonic, Y axis- Normalized


amplitude]
Centre for Electronics
Design

and Technology

Results for 40Hz(3-level operation)Configuration I

Pole voltages and phase voltage [Y


axis 100V/division, X axis- 0.02s/div]

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis0.01s/div]

FFT of the pole voltage waveform [X axisorder of harmonic, Y axis- Normalized


amplitude]

Centre for Electronics Design


and Technology

Results for 40Hz(3-level operation)Configuration I

Phase voltage and no load phase current


[Y axis voltage 50V/div, current 1A/div, X
axis- 0.01s/div]

Phase voltage and no load phase current [Y


axis voltage 100V/div, current 1A/div,
0.01s/div]

FFT of the phase voltage waveform [X axisorder of harmonic, Y axis- Normalized


amplitude]

Centre for Electronics Design


and Technology

Results for 46Hz(Overmodulation)Configuration I

Pole voltages and phase voltage [Y axis100V/div, X axis- .02s/div]

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis0.01s/div]

FFT of the pole voltage waveform [X axisorder of harmonic, Y axis- Normalized


Centre foramplitude]
Electronics Design

and Technology

Results for 46Hz(Overmodulation)Configuration I

Phase voltage and no load phase


current Y axis -50V/div, current 1A/div,
X axis- 0.01s/div]

Phase voltage and no load phase current


[Y axis voltage 100V/div, current 1A/div, X
axis- 0.01s/div]

FFT of the phase voltage waveform [X axisorder of harmonic, Y axis- Normalized


amplitude]
Centre for
Electronics Design

and Technology

Results for 48Hz(Overmodulation)Configuration I

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis
0.01s/div]

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis
0.01s/div]

FFT of the pole voltage waveform [X axisorder of harmonic, Y axis- Normalized


Centre amplitude]
for Electronics Design

and Technology

Results for 48Hz(Overmodulation)Configuration I

Phase voltage and no load phase


Phase voltage and no load phase current [Y
current [Y axis voltage 100V/div, X axis voltage 100V/div, current 1A/div, X
axis 0.01s/div]
axis 0.01s/div]

FFT of the phase voltage waveform [X axisorder of harmonic, Y axis- Normalized


amplitude]

Centre for Electronics Design


and Technology

Results for 50Hz (6step mode)-Configuration


I

Pole voltages and phase voltage [Y


axis 100V/div, X axis 0.02s/div]

Pole voltages and phase voltage


[Y axis 100V/div, X axis
0.01s/div]

FFT of the pole voltage waveform [X axis- order


of harmonic, Y axis- Normalized amplitude]

Centre for Electronics Design


and Technology

Results for 50Hz (6step mode)-Configuration


I

Phase voltage and no load phase


current [Y axis 100V/div, X axis
0.01s/div]

Phase voltage and no load phase current [Y


axis voltage 100V/div, current 1A/div, X
axis 0.01s/div]

FFT of the phase voltage waveform [X axisorder of harmonic, Y axis- Normalized


amplitude]

Centre for Electronics Design


and Technology

Acceleration from 20-30Hz (two-level


to three-level transition)

Phase voltage and no load phase current [Y Phase voltage and no load phase current [Y
axis Voltage 100V/div, current 1A/div, X
axis Voltage 100V/div, current 1A/div, X
axis 0.05s/div]
axis 0.05s/div]

Centre for Electronics Design


and Technology

Acceleration from 40-50Hz (linear


range to 6 step through
overmodulation)

Smooth transition of phase voltage and


phase current [Y axis Voltage 100V/div,
current 1A/div, X axis 0.05s/div]

Smooth transition phase voltage and


phase current [Y axis Voltage 100V/div,
current 1A/div, X axis 0.05s/div]

Centre for Electronics Design


and Technology

Speed Reversal from -20 to 20Hz

The profile of the phase current during


speed reversal when the system is given
a reversal command from 20Hz to -20 Hz
[Y axis current 1A/div, X axis 1s/div]

The profile of the phase current during


speed reversal when the system is given
a reversal command from 20Hz to -20 Hz
[Y axis current 1A/div, X axis 1s/div]

Centre for Electronics Design


and Technology

Upper cascaded structure

Centre for Electronics Design


and Technology

Configuration II with switching states of CMV


group C

Centre for Electronics Design


and Technology

Possible switching states of inverter II


given the switching state of Inverter I
State of any phase
of inverter- I

Possible states of
inverter- II

+,0,

+,0

+,

Centre for Electronics Design


and Technology

The space vector hexagon for


Configuration II

The hexagonal structure has


no multiplicity in switching
states for any phasor
location but zero phasor.
The zero phasor has 3
switching states.

Centre for Electronics Design


and Technology

Simulation and
experimental results for
configuration II

Centre for Electronics Design


and Technology

20Hz(2-level operation)-Configuration II

Pole voltages and phase voltage [Y


axis 50V/division, X axis0.016s/div]

Pole voltages and phase voltage [Y


axis- 50V/division, X axis0.01s/div ]

Phase voltage and no load phase current [Y Phase voltage and no load phase current [Y
axis voltage 100V/div, current 1A/div, Y axis- axis voltage 50V/div, current 1A/div, Y axis0.014s/div]
0.01s/div ]

Centre for Electronics Design


and Technology

20Hz(3-level operation)-Configuration II

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis0.01s/div]

Phase voltage and no load phase


current [ Y axis voltage 50V/div,
current 1A/div, X axis-0.01s/div]

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis0.005s/div ]

Phase voltage and no load phase current [Y


axis voltage 50V/div, current 1A/div,
0.005s/div ]

Centre for Electronics Design


and Technology

46Hz(Overmodulation) operationConfiguration II

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis0.01s/div]

Phase voltage and no load phase current [ Y


axis voltage 50V/div, current 1A/div, X axis0.006s/div]

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis0.005s/div ]

Phase voltage and no load phase current [Y


axis voltage 50V/div, current 1A/div, X axis0.005s/div]

Centre for Electronics Design


and Technology

48Hz(Overmodulation) operationConfiguration II

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis
0.01s/div]

Pole voltages and phase voltage [Y


axis voltage 100V/div, X axis
0.005s/div]

Phase voltage and no load phase current [Y Phase voltage and no load phase current [Y
axis voltage 50V/div, current 1A/div, X axis axis voltage 50V/div, current 1A/div, X axis
0.01s/div]
0.005s/div ]

Centre for Electronics Design


and Technology

50Hz(6-step mode) operation-Configuration


II

Pole voltages and phase voltage


[Y axis 100V/div, X axis
0.01s/div]

Pole voltages and phase voltage


[Y axis 100V/div, X axis
0.005s/div ]

Phase voltage and no load phase current [Y Phase voltage and no load phase current [Y
axis voltage 50V/div, current 1A/div, X axis axis voltage 100V/div, current 1A/div, X axis
0.005s/div ]
0.01s/div]

Centre for Electronics Design


and Technology

Acceleration from 20-30Hz (two-level


to three-level transition)

Phase voltage and no load phase current [Y


axis Voltage 100V/div, current 1A/div, X
axis 0.025s/div]

Centre for Electronics Design


and Technology

Acceleration from 40-50Hz (linear


range to 6 step through
overmodulation)

Smooth transition phase voltage and phase


current [Y axis Voltage 50V/div, current
1A/div, X axis 0.025s/div]

Centre for Electronics Design


and Technology

Reversal from -20 to


20Hz

The profile of the phase current during


speed reversal when the system is given a
reversal command from 20Hz to -20 Hz [Y
axis current 1A/div, X axis 1s/div]

Centre for Electronics Design


and Technology

Salient features of the drive


schemes

Only 18 switches are needed for a CMV eliminated 3level drive scheme compared to the previous
configuration which has 24 switches.
CMV is eliminated in the entire modulation range upto
6 step mode.
Only two isolated dc-links are needed.
An SVPWM algorithm which uses only sampled
amplitude of the reference signals for switching time
computation is used which makes the implementation
faster compared to the conventional methods.

Centre for Electronics Design


and Technology

A Four-level inverter scheme with


Common mode voltage elimination
and capacitor voltage balancing for
an open-end winding Induction
machine

Centre for Electronics Design


and Technology

Seven- level power circuit

Six conventional two-level inverters and 6 isolated supplies to get a 7-level


structure.
Inverter A is a four -level inverter formed by cascading 3 two-level
inverters.
Motor is fed from both ends.

Centre for Electronics Design


and Technology

CMV groups of the switching states


CMV group

Generated
CMV

Switching states

+Vdc/2

333

+4Vdc/9

332,323,233

+7Vdc/18

322,232,223,331,133,313

+Vdc/3

330,303,033,321,312,213,231,123,132,222

+5Vdc/18

320,302,230,203,023,032,311,131,113,221,212
,122

+2Vdc/9

310,301,130,103,013,031,220,202,022,211,112
,121

+Vdc/6

300,030,003,210,201,120,102,012,021,111

+Vdc/9

200,020,002,110,101,011

+Vdc/18

100,010,001

000

Centre for Electronics Design


and Technology

Four level CMV eliminated space vector


structure

4096 switching states for 127 vector locations.


Four level CMV eliminated structure formed out of 7-level structure.
Only 4 CMV groups namely D,E, F and G can form four-level structure.
E and F have 144 switching states and D and G have 100 switching states for 37
locations.

Centre for Electronics Design


and Technology

Four-level CMV eliminated scheme ( group F)

Switching states of CMV group F are selected.


Since there is no CMV, the dc links for Inverter A and Inverter B can be
connected together .
Centre for Electronics Design
and Technology

Voltage phasor locations and number of redundant


states of the CMV eliminated 4-level inverter

Centre for Electronics Design


and Technology

Switching states corresponding to the vector


locations of 60o sector C1-O-C4
Phasor
locatio
n

Switching states

O(12)

(022,022), (220,220), (202,202), (112,112),


(211,211), (121,121), (013,013),
(031,031), (103,103), (130,130),
(301,301), (310,310)

A1(8)

(310,211), (220,121), (121,022), (211,112),


(112,013), (202,103), (130,031),
(301,202)

A2(8)

(121,112), (211,202), (220,211), (130,121),


(031,022), (310,301),(022,013),
(112,103)

B1(4)

(310,112), (220,022), (211,013), (301,103)

B2(5)

(220,112), (310,202), (211, 103), (121,013),


(130,022)

B3(4)

(130,112), (121,103), (031,013),(220,202)

C1(1)

(310,013)

C2(2)

(220,013),(310,103)

C3(2)

Centre for Electronics Design


(220,103),(130,013)
and Technology

Model of the four level inverter

Centre for Electronics Design


and Technology

Phase winding connections for switching


states corresponding to phasor location O
(ZV)

Switching states are has no effect of the capacitor currents.


Centre for Electronics Design
and Technology

Two-level(2L) group switching states (phasor location


A1)

IC3= ia
IC2=ic
IC1= ia- ic

IC3= -ic
IC2= ia- ic
IC1= ia
Centre for Electronics Design
and Technology

IC3= ia- ic
IC2= ia- ic
IC1= 0

Two-level(2L) group switching states (phasor location


A1)
-Continued

IC3= ia- ic
IC2= - ic
IC1= ia

IC3= - ic
IC2= ia
IC1= ia- ic

Centre for Electronics Design


and Technology

IC3= ia- ic
IC2= ia
IC1= - ic

Two-level(2L) group switching states (phasor location


A1)
-Continued

IC3= ia
IC2= ia- ic
IC1= - ic

IC3= ia- ic
IC2= 0
IC1= ia- ic
Centre for Electronics Design
and Technology

Two-level(2L) group switching states


Vector

Switching state

DC-link Capacitor currents


IC3

IC2

IC1

Two-level(2L) group switching states


A1(1,0,-1)

(202,103)

ia

-ic

ia-ic

(310,211)

-ic

ia-ic

ia

(130,031)

ia-ic

ia-ic

(220,121)

ia-ic

-ic

ia

(301,202)

-ic

ia

ia-ic

(121,022)

ia-ic

ia

-ic

(112,013)

ia

ia-ic

-ic

(211,112)

ia-ic

ia-ic

Centre for Electronics Design


and Technology

Three-level(3L) group switching states (phasor


location B1)

IC3= ia
IC2= 0
IC1= - ic

IC3= - ic
IC2= 0
IC1= ia
Centre for Electronics Design
and Technology

Three-level(3L) group switching states (phasor


location B1)

IC3= ia- ic
IC2= 0
IC1= 0

IC3= 0
IC2= 0
IC1= ia- ic

Centre for Electronics Design


and Technology

Three-level(3L) group switching states (phasor location


B2)

IC3= ia+ ib- ic


IC2= 0
IC1= ia+ ib

IC3= ia- ic
IC2= ia+ ib
IC1= ib
Centre for Electronics Design
and Technology

IC3= ib- ic
IC2= ia+ ib
IC1= ia

Three-level(3L) group switching states (phasor location


B2)

IC3= ia+ ib
IC2= ib
IC1= ia-ic

IC3= ia+ ib
IC2= ia
IC1= ib-ic
Centre for Electronics Design
and Technology

Three-level(3L) group switching states

Vector

Switching state

DC-link Capacitor currents


IC3

IC2

IC1

Three-level(3L) group switching states


B1(2,0,-2)

B2(1,1,-2)

(310,112)

-ic

ia

(211,013)

ia

-ic

(220,022)

ia-ic

(301,103)

ia-ic

(220,112)

ia+ib-ic

ia+ib

(130,022)

ia-ic

ia+ib

ib

(310,202)

ib-ic

ia+ib

ia

(211,103)

ia+ib

ib

ia-ic

(121,013)

ia+ib

ia

ib-ic

Centre for Electronics Design


and Technology

Four-level(4L) group switching states

Phasor location
C 1
Vector
Switching state

Phasor location
C2
DC-link Capacitor currents
IC3

IC2

IC1

Four-level(4L) group switching states


C1(3,0,-3)

(310,013)

C2(2,1,-3)

(220,013)

ia+ib

ib

(310,103)

ib

ib

ia

Centre for Electronics Design


and Technology

Principle of capacitor voltage balancing


If the capacitor is sized for the reactive
current, the DC- link capacitor voltages
will not get unbalanced under no load
conditions.
Only active component of the load
causes capacitor voltage imbalance.
At any instant, active component of
the current vector is in the same
direction as that of the voltage phasor.

Projections of active component on the


axesdare
cos(), d cos(120 ),d cos(120 )

Centre for Electronics Design


and Technology

Capacitor current as a function of active


components of the motor phase currents
IC3= ia
IC2= - ic
IC3= iaic
Vector here is (1,0,1)
=30o
IC1= ia
IC2= ic
IC3= ia+ ic

Centre for Electronics Design


and Technology

Capacitor currents- Two-level(2L) group switching


states
Vector

Switching
state

DC-link Capacitor currents


IC3

IC2

IC1

Relative magnitudes
of active
components of the
phase currents

Two-level(2L) group switching states


A1(1,0,1)

(202,103)

i+a'

ic'

ia'+ic'

ib'=0,ia'=ic'

(310,211)

ic'

ia'+ic'

ia'

ib'=0,ia'=ic'

(130,031)

ia'+ic'

ia'+ic'

ib'=0,ia'=ic'

(220,121)

ia'+ic'

ic'

ia'

ib'=0,ia'=ic'

(301,202)

ic'

ia'

ia'+ic'

ib'=0,ia'=ic'

(121,022)

ia'+ic

ia'

ic'

ib'=0,ia'=ic'

(112,013)

ia'

ia'+ic'

ic'

ib'=0,ia'=ic'

(211,112)

ia'+ic'

ia'+ic'

ib'=0,ia'=ic'

Centre for Electronics Design


and Technology

Capacitor currents- Three-level(3L) group switching


states
Vector

Switching
state

DC-link Capacitor currents


IC3

IC2

IC1

Relative magnitudes
of active
components of the
phase currents

Three-level(3L) group switching states


B1(2,0,2)

B2(1,1,2)

(310,112)

ic'

ia'

ib'<ia'=ic'

(211,013)

ia'

ic'

ib'<ia'=ic'

(220,022)

ia'+ic'

ib'<ia'=ic'

(301,103)

ia'+ic'

ib'<ia'=ic'

(220,112)

ia'+ib'+ic'

ia'+ib'

ib=ia'<ic'

(130,022)

ia'+ic'

ia'+ib'

ib'

ib'=ia'<ic'

(310,202)

ib'+ic'

ia'+ib'

ia'

ib'=ia'<ic'

(211,103)

ia'+ib'
ib'
ia'+ic'
Centre for Electronics
Design
ia'+ib'and Technology
ia'
ib'+ic'

(121,013)

ib'=ia'<ic'
ib'=ia'<ic'

Capacitor currents- Four-level(4L) group switching


states

Vector

Switching
state

DC-link Capacitor currents


IC3

IC2

IC1

Relative magnitudes
of active
components of the
phase currents

Four-level(4L) group switching states


C1(3,0,3)

(310,013)

ib'=0,ia'=ic'

C2(2,1,3)

(220,013)

ia'+ib'

ib'

ib'<ia'<ic'

(310,103)

ib'

ib'

ia

ib'<ia'<ic'

Centre for Electronics Design


and Technology

Operation at sector B1- C1- C2


Vector

Switching
state

IC3

IC2

IC1

Relative
magnitud
e

B1(2,0,2)

(310,112)

ic'

ia'

ib'<ia'=ic'

(211,013)

ia'

ic'

ib'<ia'=ic'

(220,022)

ia'+ic'

ib'<ia'=ic'

(301,103)

ia'+ic'

ib'<ia'=ic'

C1(3,0,3)

(310,013)

ib'=0,ia'=i
c'

C2(2,1,3)

(220,013)

ia'+ib'

ib'

ib'<ia'<ic'

It can be seen that none of the switching


states of vector
(310,103)
ib' B1 affect
ib' the middle
ia
ib'<ia'<ic'
capacitor C2, but affects the top and bottom
capacitors.
Switching state of vector C1 do not affect
any capacitor voltages.

It can be seen that it is not possible to


operate only with DC-link.
Centre for Electronics Design
and Technology

Modified power circuit

The middle capacitor is


supplied with a DC- source of
voltage rating Vdc/6.
Now, the Capacitor
balancing problem is
between C1 and C3.
Even in this case, there are
cases where the currents of
the redundant states are not
exactly opposite.
Thus an open loop capacitor
voltage balancing scheme is
not possible.

Centre for Electronics Design


and Technology

Operation in open -loop


Vector

Switching
state

IC3

IC1

Relative
magnitude

B1(2,0,2)

(310,112)

ic'

ia'

ib'<ia'=ic'

(211,013)

ia'

ic'

ib'<ia'=ic'

(220,022)

ia'+ic'

ib'<ia'=ic'

(301,103)

ia'+ic
'

ib'<ia'=ic'

C1(3,0,3)

(310,013)

ib'=0,ia'=ic'

C2(2,1,3)

(220,013)

Complementar
pair

ib'
ib'<ia'<ic'
Capacitoria'+ib'
balancing problem is between C1
and C3.

(310,103)

ib'

ia

ib'<ia'<ic'

Even in this case there are cases where the


currents of the redundant states are not
exactly opposite.
Thus an open loop capacitor voltage
balancing scheme is not possible.

Centre for Electronics Design


and Technology

Operation in open-loop
Vector

Switching
state

IC3

IC1

Relative
magnitude

B1(2,0,2)

(310,112)

ic'

ia'

ib'<ia'=ic'

(211,013)

ia'

ic'

ib'<ia'=ic'

Complementar

(220,022)

ia'+ic'

ib'<ia'=ic'

pair

(301,103)

ia'+ic
'

ib'<ia'=ic'

C1(3,0,3)

(310,013)

ib'=0,ia'=ic'

C2(2,1,3)

(220,013)

ib'
ib'<ia'<ic'
Capacitoria'+ib'
balancing problem is between C1
and C3.

(310,103)

ib'

ia

ib'<ia'<ic'

Even in this case there are cases where the


currents of the redundant states are not
exactly opposite.
Thus an open loop capacitor voltage
balancing scheme is not possible.

Centre for Electronics Design


and Technology

Operation in open-loop
Vector

Switching
state

IC3

IC1

Relative
magnitude

B1(2,0,2)

(310,112)

ic'

ia'

ib'<ia'=ic'

(211,013)

ia'

ic'

ib'<ia'=ic'

(220,022)

ia'+ic'

ib'<ia'=ic'

(301,103)

ia'+ic
'

ib'<ia'=ic'

C1(3,0,3)

(310,013)

ib'=0,ia'=ic'

C2(2,1,3)

(220,013)

No effect

ib'
ib'<ia'<ic'
Capacitoria'+ib'
balancing problem is between C1
and C3.

(310,103)

ib'

ia

ib'<ia'<ic'

Even in this case there are cases where the


currents of the redundant states are not
exactly opposite.
Thus an open loop capacitor voltage
balancing scheme is not possible.

Centre for Electronics Design


and Technology

Operation at sector B1- C1- C2


Vector

Switching
state

IC3

IC1

Relative
magnitude

B1(2,0,2)

(310,112)

ic'

ia'

ib'<ia'=ic'

(211,013)

ia'

ic'

ib'<ia'=ic'

(220,022)

ia'+ic'

ib'<ia'=ic'

(301,103)

ia'+ic
'

ib'<ia'=ic'

ib'=0,ia'=ic'

C1(3,0,3)

(310,013)

C2(2,1,3)

(220,013)

No
Complementary
states

ia'+ib'
ib'
ib'<ia'<ic'
Capacitor
balancing problem is between C1
and C3.

(310,103)

ib'

ia

ib'<ia'<ic'

Even in this case there are cases where the


currents of the redundant states are not
exactly opposite.
Thus an open loop capacitor voltage
balancing scheme is not possible.

Centre for Electronics Design


and Technology

Closed loop control of the capacitor


voltages
V= V -V
C3

C1

If V>0 then controller


state is CH
If V=0 then controller
state is CN
If V<0 then controller
state is CL

Centre for Electronics Design


and Technology

Switching state and the corrective action


Vector

Switching state

Relative magnitudes of the


capacitor currents

Corrective action for

A1(1,0,-1)

(202,103)

IC3< IC1

CH

(310,211)

IC3= IC1

CN

(130,031)

IC3> IC1

CL

(220,121)

IC3> IC1

CL

(301,202)

IC3< IC1

CH

(121,022)

IC3> IC1

CL

(112,013)

IC3= IC1

CN

(211,112)

IC3= IC1

CN

(310,112)

IC3= IC1

CN

(211,013)

IC3= IC1

CN

(220,022)

IC3> IC1

CL

(301,103)

IC3< IC1

CH

(220,112)

IC3> IC1

CL

(130,022)

IC3> IC1

CL

(310,202)

IC3> IC1

CL

(211,103)

IC3< IC1

CH

(121,013)

IC3< IC1

CH

C1(3,0,-3)

(310,013)

IC3= IC1

CN

C2(2,1,-3)

(220,013)

IC3> IC1

CL

B1(2,0,-2)

B2(1,1,-2)

(310,103)

I <for
I Electronics DesignC
Centre
and Technology
C3

C1

Simulation results

Centre for Electronics Design


and Technology

Steady state results-Two- level operation


VAO

VAA

VAA

VAO

Ia

Controlle
r state
Pole voltages, phase voltage and
controller state (X- axis 50 ms/div, Y axis100V/div)

Phase voltage and no load phase current (Xaxis 50 ms/div, Y axis- voltage- 100V/div,
current- 1A/div

FFT of the phase voltage (X axis- order of


harmonics, Y axis- normalized magnitude)

Centre for Electronics Design


and Technology

Steady state results -Three-level operation


VAO
VAA

VAA
VAO
Controlle
r state
Pole voltages, phase voltage and
controller state (X axis- 50 ms/div, Y axis100V/div)

Ia

Phase voltage and no load phase current (X


axis- 50 ms/div, Y axis- voltage- 100V/div,
current- 1A/div )

FFT of the phase voltage (X axis- order of


harmonics, Y axis- normalized magnitude)

Centre for Electronics Design


and Technology

Steady state results -Four-level operation


VAO
VAA

VAA
VAO
Controlle
r state
Pole voltages, phase voltage and
controller state (X axis- 10 ms/div, Y axis200V/div)

Ia

Phase voltage and no load phase current (X


axis- 10 ms/div, Y axis- voltage- 100V/div,
current- 2A/div)

FFT of the phase voltage (X axis- order of


harmonics, Y axis- normalized magnitude)

Centre for Electronics Design


and Technology

Steady state results-18-step operation


VAO
VAA

VAA
VAO
Controlle
r state
Pole voltages, phase voltage and
controller state (X axis- 10 ms/div, Y axis200V/div)

Ia

Phase voltage and no load phase current (X axis20 ms/div, Y axis- voltage- 100V/div, current2A/div)

FFT of the phase voltage (X axis- order of


harmonics, Y axis- normalized magnitude)

Centre for Electronics Design


and Technology

Capacitor voltage balancing during two-level


operation

During two-level operation, since the


second source is across the C2
capacitor, the power is directly delivered
to the load from the source.
Again, all the locations in the two-level
case have complementary switching
pairs.
So chance of getting large unbalanced
state is minimal.
(X axis- 0.2 s/div, Y axis- 2V/div)

Centre for Electronics Design


and Technology

Capacitor voltage balancing during threelevel operation


Normal operation

X axis- 0.2 s/div, Y axis- 20V/div

When the controller is


disabled momentarily and
enabled again

X axis- 0.2 s/div, Y axis- 20V/div

Centre for Electronics Design


and Technology

Capacitor voltage balancing during four-level


operation
Normal operation

(X axis- 0.2 s/div, Y axis- 5V/div)

When the controller is


disabled momentarily and
enabled again

(X axis- 0.1 s/div, Y axis- 20V/div)

Centre for Electronics Design


and Technology

Capacitor voltage balancing during 18-step


mode of operation
Normal operation

(X axis- 0.2 s/div, Y axis- 5V/div)

When the controller is


disabled momentarily and
enabled again

(X axis- 0.1 s/div, Y axis- 20V/div)

Centre for Electronics Design


and Technology

Experimental results

Centre for Electronics Design


and Technology

Two-level operation
VAO
VAO
VAA
Controller
state

(X- axis 25ms/div, Y- axis- trace 1- 50V/div,


trace 2- 50V/div, trace 3 - 50V/div, trace 41V/div)

VAA
VC3,VC1
Ia
(X- axis 25ms/div, Y- axis- trace 1- 50V/div,
trace 2- 10V/div, trace 3- 10V/div, trace 4500mA/div)
Centre
for Electronics Design

and Technology

Three-level operation
VAO
VAO
VAA
Controller
state

(Y axis -Trace 1- 50V/div, Trace 2 - 50V/div, trace


3-100V/div, trace 4- 1V/div, X axis - 10ms/div)

VAA
VC3,VC1
Ia
(X- axis 10ms/div, Y- axis- trace 1- 50V/div,
trace 2- 10V/div, trace 3- 10V/div, trace 4500mA/div)

Centre for Electronics Design


and Technology

Four-level operation
VAO
VAO
VAA
Controller
state
(X- axis 5ms/div, Y- axis- trace 1- 50V/div, trace
2- 50V/div, trace 3- 100V/div, trace 4- 1V/div)

VAA
VC3,VC1
Ia
(X- axis 10ms/div, Y- axis- trace 1- 100V/div,
trace 2- 10V/div, trace 3- 10V/div, trace 4500mA/div)

Centre for Electronics Design


and Technology

18 step operation
VAO
VAO
VAA
Controller
state
(X- axis 5ms/div, Y- axis- trace 1- 50V/div, trace
2- 50V/div, trace 3- 50V/div, trace 4- 1V/div)

VAA
VC3,VC1
Ia
(X- axis 10ms/div, Y- axis- trace 1- 100V/div,
trace 2- 10V/div, trace 3- 10V/div, trace 4500mA/div)

Centre for Electronics Design


and Technology

Corrective action of the controller when the control


is disabled and enabled again-Three-level operation

VC3,VC1

VAA
(X- axis 250ms/div, Y- axis- trace 120V/div, trace 2- 20V/div, trace 3-500mA/div)

Centre for Electronics Design


and Technology

Corrective action of the controller when the control


is disabled and enabled again-Four-level operation

VC3,VC1

VAA
(X- axis 250ms/div, Y- axis- trace 120V/div, trace 2- 20V/div, trace 3
500mA/div)

Centre for Electronics Design


and Technology

Corrective action of the controller when the control


is disabled and enabled again-18 step operation

VC3,VC1

VAA
(X- axis 250ms/div, Y- axis- trace 120V/div, trace 2- 20V/div, trace 3
500mA/div)

Centre for Electronics Design


and Technology

Acceleration from three-level operation


to four-level operation

Phase voltage and phase current (X axis100ms/div, Y axis- trace 1- 50V/div, trace 21A/div

Centre for Electronics Design


and Technology

Salient features of the drive


schemes

A four-level CMV eliminated drive scheme using 6 twolevel inverters is proposed. The scheme needs 36
switches.
CMV is eliminated in the entire modulation range upto 6
step mode.
The capacitor balancing is not possible since all the
locations do not have redundant switching states with
opposite/no effect on the capacitor voltages.
A closed loop capacitor voltage balancing scheme is
implemented. This achieves the capacitor balancing
and thus needs only two-isolated DC- sources.

Centre for Electronics Design


and Technology

A Reduced Five-level
inverter scheme for an
open- end winding Induction
machine

Centre for Electronics Design


and Technology

A five-level inverter
circuit

One 3-level NPC inverter from one side and a 2-level inverter from the
other side.
The devices of the two-level inverter has to withstand the whole DC-link
voltage
Two isolated supplies are used.
Centre for Electronics Design
and Technology

Space vector locations for individual


inverters
Inverter I

Inverter II

27 switching states for 19


8 switching states for 7
locations
locations
27 Together they constitute a five-level
structure with 216 switching states for 61
locations
Centre for Electronics Design
and Technology

One leg of the power circuit for the


five- level inverter scheme
Voltage
level

Inverter
I

Inverter
II

+Vdc/2

S11

S2

+Vdc/4

S12&S13

S2

S14

S2

S11

S1

-Vdc/4

S12&S13

S1

-Vdc/2

S14

S1

Centre for Electronics Design


and Technology

Space vector structure generated by the


five-level scheme

216 switching states corresponding to the 61 vector locations.


Multiplicity is very less compared to the 5- level structure given in the
first scheme, which has a multiplicity of 729 for 61 vector locations.
But still high as compared to conventional NPC inverter scheme
where the number of switching states are 125 for 61 locations.
Centre for Electronics Design
and Technology

Comparison with conventional Five-level


schemes
Configuration
Number of Number of
Number
Number of
controlled
switches

power
diodes

capacitor
s

DC sources

MPC (Multi-point clamped)

24

18(36)

Cascaded H- bridge

24

Nil

Cascaded structure with two 2level and one 3-level NPC


structure

24

Flying capacitor topology

24

Nil

1+9
capacitor
s
(4+18
cap)

Open-end winding (symmetric


case)

24

12

Open-end winding
(asymmetric-two-level on one
side)

12+6

3(4)

Centre for Electronics Design


and Technology

Challenges in implementation

If isolated supplies are used from both sides, then


there will be phase opposition of the DC-sources
which will cause voltage variations in DC- links.
One solution is to use the same DC- link for
inverters of both the side thereby avoiding
subtraction. But, if isolation is not provided, there
will be huge triplen currents through the phases.
This triplen currents has to be taken care of.

Centre for Electronics Design


and Technology

Power circuit for the five- level inverter


scheme

One 3-level NPC inverter from one side and a 2-level inverter from the
other side.
The devices of the two-level inverter has to withstand the whole DC-link
voltage
Two isolated supplies are used.
By using Sine-triangle modulation
scheme,
Centre for Electronics
Designthe CMV is eliminated in an
average sense
and Technology

Five-level sine-triangle modulation


Triangle 1

Triangle 2
(Primary
triangle)

Triangle 2

Triangle 4

Centre for Electronics Design


and Technology

CMV elimination in an average


sense

Sine triangle modulation scheme is used for modulation


Since the pole voltages are equal to the reference sinusoids in an
average sense, the sum (VAO+VBO+VCO)= (Vas+Vbs+Vcs) in an
average sense.
For a balance three-phase system, (Vas+Vbs+Vcs) =0

By definition, VCM= (VAO+VBO+VCO)/3

Therefore, VCM =0 in the average sense.

Centre for Electronics Design


and Technology

CMV elimination in an average


sense
(n 1)
Vas VmSin t

2
)
3
4
Vcs VmSin( t
)
3
Vbs VmSin( t

Ts(n 1)
Vdc
T (n 1)
Tbs Vbs s
Vdc
T (n 1)
Tcs Vcs s
Vdc
Tas Vas

Tga Tas [I a

] TS
2
(n 1)
Tgb Tbs [Ib
] TS
2
(n 1)
Tgc Tcs [I c
] TS
2

Vdc
n 1
[Tga TS (
I a)]
Ts(n 1)
2
Vdc
n 1
VBO(avg)
[Tgb TS (
I b)]
Ts(n 1)
2
and
Vdc
n 1
VCO(avg)
[Tgc TS (
I c)]
Ts(n 1)
2
VAO(avg)

Centre for Electronics Design


and Technology

CMV elimination in an average


V
1
n 1
n 1
sense

[T (I
) T T (I
) T
3 T (n 1)
2
2

VCM(avg)

dc

as

bs

n 1
n 1
n 1
n 1
) TS+TS (
I a ) TS (
I b) TS (
I c)]
2
2
2
2
Vdc
3(n 1)
1

[Tas Tbs Tcs (I a I b I c ) TS
TS
3 Ts(n 1)
2
3(n 1)
TS
(I a I b I c ) TS]
2
Vdc
1

[T T T ]
3 Ts(n 1) as bs cs
Tcs (I c

For a balanced system

Tas Tbs Tcs Vas Vbs Vcs

(n 1)Ts
0
Vdc

Vdc
1
VCM(avg)
[T T T ] 0
3 Ts(n 1) as bs cs
Centre for Electronics Design
and Technology

V/f control scheme

Centre for Electronics Design


and Technology

Simulation results

Centre for Electronics Design


and Technology

20Hz operation- steady state results

VAO
VAA

VAA
VAO

Ia
Icm
Trace 1- Phase voltage, trace 2- no
load phase current, trace 3- common
mode current (X axis- 0.01s/div,Y
axis- 10V/div,1A/div)

VCM
Trace1-pole voltage of inverter I, trace
2- phase voltage, trace 3- pole voltage
of inverter II, trace 4- common mode
voltage (X axis- 0.01s/div, Y axis20V/div)

Centre for Electronics Design


and Technology

40Hz operation- steady state results


VAO
VAA

VAA
VAO

Ia
Icm
Trace 1- Phase voltage, trace 2- no
load phase current, trace 3- common
mode current (X axis- 0.01s/div,Y
axis- 20V/div,1A/div)

VCM

Trace1-pole voltage of Inverter I, trace


2- phase voltage, trace 3 pole voltage
of Inverter II, trace 4- common mode
voltage (X axis- 0.01s/div, Y axis40V/div)

Centre for Electronics Design


and Technology

50Hz operation- steady state results


VAO
VAA

VAA
VAO

Ia

VCM

Icm
Trace 1- Phase voltage, trace 2- no
load phase current, trace 3- common
mode current (X axis- 0.01s/div,Y
axis- 20V/div,1A/div)

Trace1-pole voltage of Inverter I, trace


2- phase voltage, trace 3- pole voltage
of Inverter II, trace 4- common mode
voltage (X axis- 0.01s/div, Y axis40V/div)

Centre for Electronics Design


and Technology

Transient results
Phase voltage, no load phase current
and common mode current while the
machine is accelerated from 20Hz to
30Hz.

Trace 1- Phase voltage, trace 2phase current, trace 3- common


mode current (X axis- 0.05s/div,Y
axis- 20V/div,1A/div)

Phase voltage, no load phase


current and common mode
current during speed reversal(20Hz to 20Hz

Trace 1- Phase voltage, trace 2phase current, trace 3- common


mode current (X axis- 0.05s/div,Y
axis- 20V/div,1A/div)

Centre for Electronics Design


and Technology

Experimental results

Centre for Electronics Design


and Technology

20Hz operation- steady state results

VAO

VAA

VAA

VBB

VAO

VCC

Ia
Trace 1- pole voltage of Inverter II (X
axis-10ms/div,Y axis- 50V/div), trace
2- pole voltage of Inverter II (X axis10ms/div,Y axis- 50V/div), trace 3phase voltage(X axis-10ms/div,Y
axis- 100V/div), trace 4- no load
phase current(X axis-10ms/div,Y
axis- 1A/div)

VCM
Trace1-pole voltage of inverter I, trace
2- phase voltage, trace 3- pole voltage
of inverter II, trace 4- common mode
voltage (X axis- 0.01s/div, Y axis50V/div)

Centre for Electronics Design


and Technology

20 Hz FFT of the pole voltages and phase


voltage

FFT of Pole voltage of inverter I

FFT of Pole voltage of inverter II

(X axis-harmonic
order, Y axisRelative
magnitude
normalized to the
phase voltage
fundamental)
FFT of phase voltage
Centre for Electronics Design
and Technology

40Hz operation- steady state results

VAO

VAA

VAA

VBB

VAO

VCC

Ia

VCM

Trace 1- pole voltage of Inverter II


(X axis-10ms/div,Y axis- 50V/div),
trace 2- pole voltage of Inverter II (X
axis-10ms/div,Y axis- 50V/div), trace
3-phase voltage (X axis-10ms/div,Y
axis- 100V/div), trace 4- no load
phase current (X axis-10ms/div,Y
axis- 1A/div)

Trace1-pole voltage of inverter I, trace 2- phase


voltage, trace 3- pole voltage of inverter II, trace
4- common mode voltage (X axis- 0.01s/div, Y
axis- 50V/div)

Centre for Electronics Design


and Technology

40 Hz FFT of the pole voltages and phase


voltage

FFT of Pole voltage of inverter I

FFT of Pole voltage of inverter II


(X axis-harmonic
order, Y axisRelative
magnitude
normalized to the
phase voltage
fundamental)

FFT of phase voltage


Centre for Electronics Design
and Technology

50Hz operation- steady state results

VAO

VAA

VAA

VBB

VAO

VCC

Ia

VCM

Trace 1- pole voltage of Inverter II


(X axis-10ms/div,Y axis- 50V/div),
trace 2- pole voltage of Inverter II (X
axis-10ms/div,Y axis- 50V/div), trace
3-phase voltage (X axis-10ms/div,Y
axis- 100V/div), trace 4- no load
phase current (X axis-10ms/div,Y
axis- 1A/div)

Trace1-pole voltage of inverter I, trace 2- phase


voltage, trace 3- pole voltage of inverter II, trace
4- common mode voltage (X axis- 0.01s/div, Y
axis- 50V/div)

Centre for Electronics Design


and Technology

50 Hz FFT of the pole voltages and phase


voltage

FFT of Pole voltage of inverter I

FFT of Pole voltage of inverter II

(X axis-harmonic
order, Y axisRelative
magnitude
normalized to the
phase voltage
fundamental)
FFT of phase voltage
Centre for Electronics Design
and Technology

Triplen current in the phase current at the no


load current

Triplen current (trace 1) and phase current


(trace 2) at modulation index 1(X axis5ms/div,Y axis- 1A/div)
Centre for Electronics Design
and Technology

Transient results acceleration and Speed


reversal
VAA

Ia

Phase voltage (trace 1- X axis5ms/div,Y axis- 50V/div) and phase


current (trace 2- X axis- 5ms/div,Y
axis- 1A/div) during the acceleration
from modulation index 0.4 to
modulation index 0.8

Phase voltage (trace 1- X axis- 5ms/div,Y


axis- 50V/div) and phase current (trace 2- X
axis- 5ms/div,Y axis- 2A/div) during speed
reversal

Centre for Electronics Design


and Technology

Salient features of the drive


schemes

The scheme needs a conventional three- level NPC inverter on


one side and a two-level inverter.
The DC- link voltage requirement is only half compared to the
conventional schemes.
Only two isolated dc-links are needed.
The common mode voltage is suppressed in an average sense
using sine- triangle modulation technique.
Hence isolated power supplies are not needed.
Inverter II (the two-level inverter) is always in square wave
operation irrespective of the modulation index.
This scheme can be extended to higher level by only changing
inverter I.

Centre for Electronics Design


and Technology

Publications

S. Figarado, T. Bhattacharya, G. Mondal and K. Gopakumar,


Three-level inverter scheme with reduced power device count for
an induction motor drive with common-mode voltage elimination
IET Power Electron., 2008, Vol. 1, No. 1, pp. 8492.
Sheron Figarado, K. Gopakumar*, Gopal Mondal, K. Sivakumar,N.S
Dinesh, Three-Level Inverter Fed Open- end Winding IM Drive with
Common Mode Voltage Elimination and Reduced Power Device
Count The 33rd Annual Conference of the IEEE Industrial
Electronics Society (IECON), Nov. 5-8, 2007, Taipei, Taiwan
Sheron Figarado, K. Sivakumar, Rijil Ramchand,Anandarup
das,Chantan Patel and K. Gopakumar, A Five-level inverter
scheme for an open- end winding Induction machine drive with
less number of switches. Accepted in IET Power Electronics,UK.

Centre for Electronics Design


and Technology

Thank You

Centre for Electronics Design


and Technology