The Von Neumann Architecture

Chapter 5.1-5.2

Von Neumann
Architecture

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Designing Computers

CMPUT101
Introduction to
Computing

All computers more or less based on the same

basic design, the Von Neumann Architecture!

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CMPUT101
Introduction to
Computing

The Von Neumann Architecture

Model for designing and building computers,

based on the following three characteristics:
1) The computer consists of four main subsystems:

Memory
ALU (Arithmetic/Logic Unit)
Control Unit
Input/Output System (I/O)

2) Program is stored in memory during execution.

3) Program instructions are executed sequentially.

The Von Neumann Architecture

Bus
Processor (CPU)
Memory

Control Unit
ALU

Store data and program

Execute program
Do arithmetic/logic operations
requested by program

CMPUT101 Introduction to Computing

Input-Output

Communicate with
"outside world", e.g.
Screen
Keyboard
Storage devices
...
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CMPUT101
Introduction to
Computing

Subsystem
Memory
Memory, also
called RAM (Random Access Memory),
Consists of many memory cells (storage units) of a fixed
size.
Each cell has an address associated with it: 0, 1,
All accesses to memory are to a specified address.
A cell is the minimum unit of access (fetch/store a
complete cell).
The time it takes to fetch/store a cell is the same for all
cells.

When the computer is running, both

Program
Data (variables)

are stored in the memory.

RAM

(c) Yngvi Bjornsson

CMPUT101
Introduction to
Computing

Need to distinguish between

the address of a memory cell

and the content of a memory
cell

0000000000000001

Memory width (W):

How many bits is each memory
cell, typically one byte (=8 bits)

0
1
2

Address width (N):

How many bits used to
represent each address,
determines the maximum
memory size = address space
If address width is N-bits, then
address space is 2N (0,1,...,2N-1)

1 bit

2N
...

2N-1

Memory Size / Speed

(c) Yngvi Bjornsson

CMPUT101
Introduction to
Computing

Typical memory in a personal computer (PC):

64MB 2GB n above

Memory sizes:
Kilobyte (KB) = 210 =
1,024 bytes ~ 1 thousand
Megabyte(MB) = 220 =
1,048,576 bytes ~ 1 million
Gigabyte (GB) = 230 = 1,073,741,824 bytes ~ 1 billion

Memory Access Time (read from/ write to memory)

50-75 nanoseconds (1 nsec. = 0.000000001 sec.)

RAM is
volatile (can only store when power is on)
relatively expensive

Operations on Memory

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CMPUT101
Introduction to
Computing

Fetch (address):
Fetch a copy of the content of memory cell with the
specified address.
Non-destructive, copies value in memory cell.

Store (address, value):

Store the specified value into the memory cell specified
by address.
Destructive, overwrites the previous value of the
memory cell.

The memory system is interfaced via:

Memory Address Register (MAR)
Memory Data Register (MDR)
Fetch/Store signal

Structure of the Memory Subsystem

MAR

MDR
F/S

Memory
decoder
circuit

Fetch/Store
controller

Fetch(address)
Load address into MAR.
Decode the address in MAR.
Copy the content of memory cell
with specified address into
MDR.

Store(address, value)
...

CMPUT101 Introduction to Computing

Load the address into MAR.

Load the value into MDR.
Decode the address in MAR
Copy the content of MDR into
memory cell with the specified
address.
(c) Yngvi Bjornsson

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CMPUT101
Introduction to
Computing

Input/Output
Handles devicesSubsystem
that allow the computer
system to:

Communicate and interact with the outside world

Screen, keyboard, printer, ...

Store information (mass-storage)

Hard-drives, floppies, CD, tapes,

Mass-Storage Device Access Methods:
Direct Access Storage Devices (DASDs)
Hard-drives, floppy-disks, CD-ROMs, ...

Sequential Access Storage Devices (SASDs)

Tapes (for example, used as backup devices)

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I/O Controllers

(c) Yngvi Bjornsson

CMPUT101
Introduction to
Computing

Speed of I/O devices is slow compared to RAM

RAM
~ 50 nsec.
Hard-Drive ~ 10msec. = (10,000,000 nsec)

Solution:

I/O Controller, a special purpose processor:

Has a small memory buffer, and a control logic to

control I/O device (e.g. move disk arm).
Sends an interrupt signal to CPU when done
read/write.

Data transferred between RAM and memory

buffer.
Processor free to do something else while I/O
controller reads/writes data from/to device into
I/O buffer.

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Structure of the I/O Subsystem

(c) Yngvi Bjornsson

Data from/to memory

CMPUT101
Introduction to
Computing

Interrupt signal (to processor)

I/O controller
I/O Buffer
Control/Logic

I/O device

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The ALU Subsystem

(c) Yngvi Bjornsson

CMPUT101
Introduction to
Computing

The ALU (Arithmetic/Logic Unit) performs

mathematical operations (+, -, x, /, )
logic operations (=, <, >, and, or, not, ...)

In today's computers integrated into the CPU

Consists of:
Circuits to do the arithmetic/logic operations.
Registers (fast storage units) to store intermediate
computational results.
Bus that connects the two.

Structure of the ALU

Registers:
Very fast local memory cells, that
store operands of operations and
intermediate results.
CCR (condition code register), a
special purpose register that
stores the result of <, = , >
operations

ALU circuitry:

R0
R1
R2

Rn

Contains an array of circuits to

do mathematical/logic
operations.

ALU circuitry

Bus:
Data path interconnecting the
registers to the ALU circuitry.
CMPUT101 Introduction to Computing

GT EQ LT
(c) Yngvi Bjornsson

14

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CMPUT101
Introduction to
Computing

The
Control
Unit
Program
is stored
in memory
as machine language instructions, in binary

The task of the control unit is to execute

programs by repeatedly:
Fetch from memory the next instruction to be
executed.
Decode it, that is, determine what is to be done.
Execute it by issuing the appropriate signals to
the ALU, memory, and I/O subsystems.
Continues until the HALT instruction

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CMPUT101
Introduction to
Computing

Machine Language Instructions

A machine language instruction consists of:

Operation code, telling which operation to perform
Address field(s), telling the memory addresses of
the values on which the operation works.

Example: ADD X, Y (Add content of memory

locations X and Y, and store back in memory location Y).
Assume: opcode for ADD is 9, and addresses X=99,
Y=100

Opcode (8 bits) Address 1 (16 bits)

00001001 0000000001100011

Address 2 (16 bits)

0000000001100100

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CMPUT101
Introduction to
Computing

Instruction Set Design

Two different approaches:

Reduced Instruction Set Computers (RISC)

Instruction set as small and simple as possible.
Minimizes amount of circuitry --> faster
computers

Complex Instruction Set Computers (CISC)

More instructions, many very complex
Each instruction can do more work, but require
more circuitry.

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CMPUT101
Introduction to
Computing

Typical
Machine Instructions
Notation:
We use X, Y, Z to denote RAM cells
Assume only one register R (for simplicity)
Use English-like descriptions (should be binary)

Data Transfer Instructions

LOAD X

Load content of memory location X to

STORE X

Load content of R to memory location

MOVE X, Y Copy content of memory location X to

loc. Y

(not absolutely necessary)

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Machine Instructions (cont.)

CMPUT101
Introduction to
Computing

Arithmetic

ADD X, Y, Z CON(Z) = CON(X) + CON(Y)

ADD X, Y
CON(Y) = CON(X) + CON(Y)
ADD X
R = CON(X) + R
similar instructions for other operators, e.g.
SUBTR,OR, ...

Compare
COMPARE X, Y

Compare the content of memory cell X to the content

of memory cell Y and set the condition codes (CCR)
accordingly.
E.g. If CON(X) = R then set EQ=1, GT=0, LT=0

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CMPUT101
Introduction to
Computing

Machine Instructions (cont.)

Branch
JUMP X

Load next instruction from

memory loc. X

JUMPGT X

Load next instruction from memory

loc. X
only if GT flag in CCR is set,
otherwise load
statement from next
sequence loc. as
usual.
JUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQ

Control
HALT

Stop program execution.

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Example

CMPUT101
Introduction to
Computing

Pseudo-code: Set A to B + C
Assuming variable:
A stored in memory cell 100, B stored in
memory cell 150, C stored in memory cell 151

Machine language (really in binary)

LOAD
ADD
STORE
or
(ADD

150
151
100
150, 151, 100)

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Structure of the Control Unit

(c) Yngvi Bjornsson

CMPUT101
Introduction to
Computing

PC (Program Counter):
stores the address of next instruction to fetch
IR (Instruction Register):
stores the instruction fetched from memory
Instruction Decoder:
Decodes instruction and activates necessary
circuitry
PC
+1

IR

Instruction
Decoder

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CMPUT101
Introduction to
Computing

von Neumann
Architecture

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(c) Yngvi Bjornsson

CMPUT101
Introduction to
Computing

How does this all work together?

Program Execution:

PC is set to the address where the first program

instruction is stored in memory.
Repeat until HALT instruction or fatal error
Fetch instruction
Decode instruction
Execute instruction

End of loop

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CMPUT101
Introduction to
Computing

Program
Execution
(cont.)
Fetch phase
PC --> MAR
Fetch signal
MDR)
MDR --> IR
PC + 1 --> PC

(put address in PC into MAR)

(signal memory to fetch value into
(move value to Instruction Register)
(Increase address in program counter)

Decode Phase
IR -> Instruction decoder (decode instruction in IR)
Instruction decoder will then generate the signals to
activate the circuitry to carry out the instruction

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CMPUT101
Introduction to
Computing

Program Execution (cont.)

Execute Phase

Differs from one instruction to the next.

Example:
LOAD X (load value in addr. X into register)
IR_address -> MAR
Fetch signal
MDR --> R

ADD X
left as an exercise

27

Instruction Set for Our Von Neumann

Opcode
Operation
Meaning
Machine
(c) Yngvi Bjornsson

0000
0001
0010
0011
0100
0101
0101

LOAD X
STORE X
CLEAR X
ADD X
INCREMENT X
SUBTRACT X
DECREMENT X
COMPARE X

CON(X) --> R
R --> CON(X)
0 --> CON(X)
R + CON(X) --> R
CON(X) + 1 --> CON(X)
R - CON(X) --> R
CON(X) - 1 --> CON(X)

JUMP X
JUMPGT X
JUMPxx X
IN X
OUT X
HALT

Get next instruction from memory location X

Get next instruction from memory loc. X if GT=1
xx = LT / EQ / NEQ
Input an integer value and store in X
Output, in decimal notation, content of mem. loc. X
Stop program execution

0111
1000
1001
...
1101
1110
1111

CMPUT101
Introduction to
Computing

If CON(X) > R then GT = 1 else 0

If CON(X) = R then EQ = 1 else 0
If CON(X) < R then LT = 1 else 0

Digital Design & Computer Architecture

Dr. Robert D. Kent

Lecture 1
Von Neuman Architecture

Review Agenda
Von

Neumann Architecture

5 component design of the stored program digital

computer
the instruction cycle
Basic
Exceptions
instruction architecture
software design
hardware circuits
Digital

Design

Boolean logic and gates

Basic Combinational Circuits
Karnaugh maps
Advanced Combinational Circuits
Sequential Circuits

von Neumann Architecture

Principles
Data and instructions are both stored in the main
memory(stored program concept)
The content of the memory is addressable by location
(without regard to what is stored in that location)
Instructions are executed sequentially unless the order is
explicitly modified
The basic architecture of the computer consists of:
Computer
Data
CPU

Bus
Control

Main
Memory

von Neumann Architecture

A

more complete view of the computer system

architecture that integrates interaction (human or
otherwise) consists of:
Computer System

Computer
Input
Device

Data
CPU

Bus

Main
Memory

Output
Device

Control
Five Main Components:
1. CPU
2. Main Memory (RAM)
3. I/O Devices
4. Mass Storage
5. Interconnection network (Bus)

Bus

Bus
Secondary
Storage
Device

Another view of a digital

computer

The Instruction Cycle

The

Instruction Cycle

Basic
Intermediate
Exceptions

The Instruction Cycle - Basic

View
Once

the computer has

been started
(bootstrapped) it
continually executes
instructions (until the
computer is stopped)
Different instructions take
different amounts of time
to execute (typically)
All instructions and data are
contained in main memory

Start

Fetch
Instruction

Execute
Instruction

The Instruction Cycle - Intermediate

View
Start
A

complete instruction
consists of
operation code
addressing mode
zero or more operands
immediately available data
(embedded within the
instruction)
the address where the data
can be found in main
memory

Fetch
Instruction

Decode
Instruction

Fetch
Operand

Execute
Instruction

The Instruction Cycle Exceptions

Exceptions, or errors, may

occur at various points in the
instruction cycle, for example:

Start

Possible
Exception?

Fetch
Instruction

Possible
Exception?

Decode
Instruction

Possible
Exception?

Fetch
Operand

Possible
Exception?

Execute
Instruction

The Instruction Cycle Exceptions

Start

Exceptions, or errors, may

occur at various points in the
instruction cycle, for example:

Fetch
Instruction

Addressing - the memory does

not exist or is inaccessible

Decode
Instruction

Fetch
Operand

Execute
Instruction

The Instruction Cycle Exceptions

Exceptions, or errors, may

occur at various points in the
instruction cycle, for example:
Operation - the operation code
does not denote a valid
operation

Start

Fetch
Instruction

Decode
Instruction

Fetch
Operand

Execute
Instruction

The Instruction Cycle Exceptions

Exceptions, or errors, may

occur at various points in the
instruction cycle, for example:
Execution - the instruction logic
fails, typically due to the input
data
divide by zero
integer addition/subtraction
overflow
floating point
underflow/overflow

Start

Fetch
Instruction

Decode
Instruction

Fetch
Operand

Execute
Instruction

Instruction Architecture
Software

design
Hardware circuits

Instruction Architecture - Software

Design

Each computer CPU must be designed to accommodate and understand instructions according to
specific formats.
Examples:

All instructions must have an operation code specified

NOP
no operation
TSTST
test and set

OpCode

Instruction Architecture - Software

Design

Each computer CPU must be designed to accommodate and understand instructions according to
specific formats.
Examples:

Most instructions will require one, or more, operands

These may be (immediate) data to be used directly
or, addresses of memory locations where data will be found (including the address of yet another location)

OpCode

Operand (Address)

Instruction Architecture - Software

Design

Sometimes the instruction format requires a code, called the Mode, that specifies a particular addressing format to be distinguished from
other possible formats

direct addressing

indirect addressing

indexed addressing

relative addressing

doubly indirect addressing

etc.

OpCode

Mode

Op. (Addr.)

Mode

Op. (Addr.)

Instruction Architecture - CPU

The

CPU must be designed to accommodate the

instructions and data to be processed
I/O 1

I/O 2

I/O n

System Bus
CPU

RAM
System Bus

CU

IR
Internal
CPU Bus

PSW

Address Bus

PC

Data Bus

Regs

Control Bus

ALU

Instruction Architecture - Hardware

Circuits
Everything

that the computer can do is the result of

designing and building devices to carry out each
function no magic!

At

the most elementary level the devices are called logic

gates.
There are many possible gate types, each perform a
specific Boolean operation (e.g. AND, OR, NOT, NAND,
NOR, XOR, XNOR)

ALL

circuits, hence all functions, are defined in terms of

the basic gates.

We

apply Boolean Algebra and Boolean Calculus in order

to design circuits and then optimize our designs.

Instruction Architecture - Hardware

Circuits
Data is represented by various types of signals,
including electrical, magnetic, optical and so on. Data
moves through the computer along wires that form
the various bus networks (address, data, control) and
which interconnect the gates.
Combinations

of gates are called integrated circuits (IC).

All

computer functions are defined and controlled by

ICs of varying complexity in design. The manufacture
of these may be scaled according to size/complexity:
LSI
VLSI
ULSI

large scale integration

very large scale integration
ultra large scale integration

Instruction Architecture - CU
The

control unit must decode instructions, set up for

communication with RAM addresses and manage the
data stored in register and accumulator storages.

Each

such operation requires separate circuitry to

perform the specialized tasks.

It

is also necessary for computer experts to have

knowledge of the various data representations to be
used on the machine in order to design components that
have the desired behaviours.

Instruction Architecture - ALU

All

instructions together are called the instruction set

CISC
RISC
Each

complex instruction set

reduced instruction set

ALU instruction requires a separate circuit, although

some instructions may incorporate the circuit logic of other
instructions