Multimicroprocessor systems

As we all know a single processor system has an upper limit of its

processing capability.
A system having two microprocessor will require only lesser time to
complete the task.
The study of a system, involving several connected microprocessors, using
a certain topology to further enhance the speed of operation is called
Multimicroprocessor Architecture.
Multimicroprocessor system consist of
CPU
Numeric Data Processor ( NDP ) Or / And
Input / Output processor ( IOP )

Numeric Data Processor :

Independent Processing Unit.
Perform complicated numeric calculation in comparatively less time.
Works in coherence with the main processor.

Input / Output Processor :

Take care of I/O activities of the system.

Coprocessor

A computer processor used to supplement the function of primary processor.

First seen on mainframe computers.

Accelerate the system performance.

Operation performed :

Floating point arithmetic

Graphic & Signal processing.
String processing.
Encryption

They are Unable to fetch the code from the memory so they work under the
control of main processor .

Both microprocessor and coprocessor can execute their respective

instructions simultaneously and concurrently.
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Intel 80386 CPU w / 80387 Math Coprocessor

Architecture of 8087

Intel 8087
Numeric Processor.
Packed in 40 pin ceramic DIP package.
Available in 5 MHz, 8MHz, 10MHz versions compatible with 8086,
8088, 80186, 80188.
It adds 68 new instruction to the instruction set of 8086.
How it works :
The 8087 instruction may lie interleaved in the 8086 program, but it

is the task of 8086 to identify the 8087 instructions from the program,
send it to 8087 for further execution & after the completion of
execution cycle the result may be referred back to CPU.

Operation of 8087 does not require any software support from the
system software or operating system.
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Architecture of 8087

Two major sections:

1)
2)

Control unit
Numeric Execution unit

Control Unit :
Function :
It interface the coprocessor to the microprocessor
system data bus.
Monitors the instruction stream.
If the instruction is an ESCape (coprocessor)
instruction, the coprocessor executes it; if not the
microprocessor executes it.
It receives , decodes instructions, read and write
memory operands and executes the 8087 instruction.
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Numeric Execution Unit (NEU)

Functions :
Execute all the numeric processor instructions.
It has 8 register (80 bit) stack that holds the operands for arithmetic
instructions & the result.
Instruction either address data in specific stack data register or
uses push and pop mechanism to store and retrieve data.

Programmable shifter :
Responsible for shifting the operands during the execution of
instruction like FMUL and FDIV.
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Microcode control unit :

It generates the control signals required for the execution of
instruction.

The internal data bus is 84 bits wide including 68 bit

fraction, 15 bit exponent and a sign bit.

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Status word of 8087

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1) B busy bit

Indicates the coprocessor is busy in executing a task.

2) C3- C0 (Condition code bits)

Indicates the condition of the coprocessor.

3) TOP ( Top-of-stack (ST))

Indicates the current register addressed as the top-of-the

stack (ST). Normally register 0.

4) ES error summary

Bit is set if any unmasked error bit (PE,UE,OE, ZE, DE or

IE) is set.

5) PE precision error

Indicate the result or operand exceed the selected

precision.

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6) UE Underflow Error

Indicates a non zero result that is too small to represent

with the current precision selected.

7) OE Overflow Error

Indicates a result is too large to be represented.

8) ZE Zero Error

Indicates the divisor was zero while the dividend is a noninfinity or non zero number.

9) DE Denormalized error

Indicates that at least one of the operands is denormalized.

10) IE Invalid Error

Flag indicates errors such as those produced by taking the

square root of negative number.
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Control Word Register of 8087

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Control register

FLDCW instruction which is used to load a value into the

control register.

1)

IC Infinity Control

2)

Selects either affine ( allows positive and negative infinity)

or projective (assumes infinity is unsigned)

RC Rounding Control

Determines the type of rounding.

00
01
10
11

- round to nearest even.

- round down towards minus infinity.
- round up towards plus infinity.
- chop or truncate toward Zero.

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3) PC Precision Control

Sets the precision of the result.

00
01
10
11

-> Single precision (short)

-> Reserved
-> Double precision (long)
-> Extended precision (temporary)

4) Exception Masks

Determine whether the error indicated by the exception

affects the error bit in the status flag.

5) Zero Divide

If any non zero finite operand is divided by zero, this

exception is generated.

6) Denormalized Operand

Exception is generated if at least one of the operand or the

result is denormalized.
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Signal Description of 8087

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Pin Diagram of 8087

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1)

AD0 - AD15 :

These are time multiplexed address / data lines.

Lines carry address during T1 and data during T2 T3 Tw &T4
states.

2) A19/S6 A16/S3 :

These are time multiplexed address/ status lines.

These function in a similar way to the corresponding pins
of 8086.
S6 ,S4 & S3 are permanently high, while the S5 is
permanently low.

3) BHE / S7 :

During t1 the BHE / S7 pin is used to enable data on to the

higher byte of the 8086 data bus.
During T2 ,T3 , Tw and T4 this is a status line S7.
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4) Qs1 , Qs0 :
Qs1 , Qs0 are queue status input signals.
These enable 8087 to keep track of the instruction prefetch
queue status of the CPU, to maintain synchronism with it.
Qs1
0
0
1
1

Qs0
0
1
0
1

Queue Status
No operation.
First byte of opcode from queue
Empty Queue
Subsequent byte from queue.

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5) INT

Used to indicate that an unmasked exception has been

received during execution.

This is usually handled by 8259A.

6) BUSY

It will be set when 8087 is busy with the execution of an

allotted instruction.

7) READY

Used to inform the coprocessor that the address device will

complete the data transfer from its side and the bus is likely to be
free for the next bus cycle.
Usually this is synchronized by the clock generator 8284
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8) RESET

Used to abandon the internal activities of the coprocessor

and prepare it for further execution.

9) CLK

It provide the basic timing for the processor operation.

10) VCC

A +5V supply

11) GND

A return line for the power supply.

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12) S2 ,S1 and S0

These can be either be 8087 driven (output) or
externally driven (input) by the CPU
s2

S1

S0

Queue status

unused

Unused

Memory read

Memory write

passive
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13) RQ / GT0
The request / grant pin is used to gain control of the bus from
the host (8086/ 8088) for operand transfer.
An active low pulse of one clock duration is generated by
8087 for the host to inform it that it wants to gain control of
the local bus either for itself or for other coprocessor
connected to RQ/ GT1 pin of 8087.
The 8087 waits for the grant pulse from the host.
When it is received, it either initiates a bus cycle if the
request is for itself or else, it passes the grant pulse to
RG/GT1, if the request is for the other coprocessor.

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14) RQ / GT1
Bidirectional pin
Used by other bus masters to convey their need of the local
bus access to 8087.

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Interconnections of 8087 with 8086/ 8088

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Interface of 8087 with 80186 / 80188

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Interconnection of 8087 with CPU :

8087 can be connected with 8086 /80188 only in their maximum
mode of operation, ie only when the MN/ Mx pin of CPU is
grounded.
In maximum mode all the control signals are derived using a
separate chip known as a bus controller.
For 8086 and 80188/ 80186 the compactable bus controller are
8288 and 82188 respectively.
The busy pin of 8087 is connected with the TEST pin of the CPU.
In 8086/8088 the QS0 &QS1 lines may be directly connected to
the corresponding pins.
8259 - Programmable interrupt controller

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 In 80186 / 80188 systems these QS0 and QS1 lines are passed to
the CPU through the bus controller.
In case of 8086 / 8088 based system the RQ/ GT0 of 8087 may be
connected to RQ / GT1 of 8086/ 8088.
The clock pin of 8087 may be connected with the CPU 8086/ 8088
clock input.
The interrupt output of 8087 is routed to 8086/8088 via a
programmable interrupt controller.
The pins AD0 AD15 , RESET , A19 /S6 - A16 /S3 , BHE / S7 are
connected to the corresponding pin of 8086/8088.
In case of 80186/ 80188 system the RQ/ GT lines of 8087 are
connected with the corresponding RQ / GT lines of 82188.

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Instruction set of 8087

The execution of 8087 instruction is transparent to the
programmer.
The instructions are fetched by 8086 but are executed by
8087.
Whenever the 8086 comes across 8087 instruction, it
executes the ESCAPE instruction code to pass over the
instruction op-code and control of the local bus to 8087.
After execution the result is referred back.

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Categorization of Instruction set

1.
2.
3.
4.
5.
6.

Data transfer Instructions.

Arithmetic Instructions
Comparison Instructions
Transcendental Operations
Constant Operations.
Coprocessor Control Operations

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1)

Data Transfer Instruction

Depending on the data type handled these are further

grouped into Three :
Floating point Data Transfer
Integer Data Transfer
BCD Data Transfer

Floating Point Data Transfer

1. FLD (Load real to top of Stack)
This instruction loads a real operand to the top of stack of
the 80 bit register.
FLD ST (7)
FLD MEM

; Stack top [Reg 7]

; Stack Top [MEM]
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2) FST (Store Top of the Operand )

This instruction stores current content of the top of
stack register to the specified operand.
FST ST(7)
FST MEM

;
;

Stack top [ ST (7) ]

stack Top [MEM]

3) FXCH (exchange with Top of Stack)

This instruction exchanges the content of the top of
stack with the specified operand register.
FXCH

ST (6)

; stack top ST (6)

Integer data transfer Instruction :

1) FILD (Load integer to stack top)
This instruction loads the specified integer data
operand to the top of stack.
FILD ST(5) ; stack Top ST (5)
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2) FIST/FISTP
The instruction work in exact similar manner as FST/
FSTP except the fact that the operand are integer
operand.

BCD Data Transfer Instructions :

FBLD & FBSTP
Both work in an exactly similar manner as FLD and FSTP except
for the operand type BCD

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Arithmetic Instructions
1.
2.
3.
4.
5.
6.

FADD
FSUB
MUL
FDIV
FSQRT
FABS

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Transcendental Instructions
The operand usually are ST(0) and ST(1) or only ST(0)
FPTAN :
Instruction calculates the tangent of an angle O, where O, must

be in range from 0<= O < 900 { ST/ST(1) }

The value of O must be stored at the stack top.

FPATAN :
Instruction calculates the inverse tangent
The result is stored on the top of the stack.
The content of ST and ST(1) should follow the inequality.
0<=ST(1) < ST< infinity

F2XMI :
Instruction calculates the expression (2x - 1)
Value of x is stored at the top of the stack.
Result is stored back at the top of the stack.

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 FLY2X
It calculate ST(1) * Log2 ( ST)
Result is stored back at the top of stack.
ST must be in the range of 0 to +infinity.
ST(1) must be in the range of -infinity to +infinity.

FLY2XP1
It calculate ST(1) * log2[ (ST)+1 ]
Result is stored back on the stack top.
|ST| must lie between 0 and (1- 21/2 /2).
Value of ST(1) must lie between infinity and + infinity

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Comparison Instruction
All the comparison instructions compare the operands and modify the
condition code flags

Comparison

C3

C0

Stack Top > Source

Stack Top < Source

Stack Top = Source

Not Comparable

1
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1.

FCOM

The content of the top of stack is compared either with the

content of a memory location or with the content of another
stack register.

2. FIST

Instruction test if the content of the stack top is Zero.

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Constant Returning Instruction

1. FLDZ
Load +0.0 to stack top

2. FLDPI
Load pi(3.14) o stack top

3. FLDLG2
Load the constant Log10 2 to the stack pointer.

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Coprocessor Control Instruction

I. FINIT
II. FENI
III. FDISI
IV. FLDCW
V. FSTSW
VI. FCLEX
VII. FFREE
VIII. FNOP
IX. FWAIT
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