CIRCUIT CHARACTERIZATION

AND PERFORMANCE
ESTIMATION CONTD
Prof. N.S.Murthy,
PPKKP/UNIMAP
murthy@unimap.edu.my

02/09/16

EMT251_NSM_09

The CMOS Inverter: A First

Glance
V
DD

V in

V out
CL

CMOS Inverter
N Well

VDD

VDD

PMOS

Contacts

PMOS
In

Out
In

NMOS

Out
Metal 1

Polysilicon

NMOS
GND

Two Inverters
Share power and ground
Abut cells
VDD

Connect in Metal

CMOS Inverter
First-Order DC Analysis
V DD

V DD
Rp
V out

V out
Rn

V in 5 V DD

V in 5 0

VOL = 0
VOH = VDD
VM = f(Rn, Rp)

CMOS Inverter Load Characteristics

ID n

PMOS

Vin = 0

Vin = 2.5

Vin = 0.5

Vin = 2

Vin = 1

Vin = 1.5

Vin = 1.5
Vin = 2
Vin = 2.5

NMOS

Vin = 1
Vin = 1.5

Vin = 1

Vin = 0.5
Vin = 0
Vout

CMOS Inverter VTC

NMOS off
PMOS res

2.5

Vout

NMOS s at
PMOS res

1.5

NMOS sat
PMOS sat

0.5

NMOS res
PMOS sat

0 .5

1 .5

NMOS res
PMOS off
2 .5

Vin

Determining VIH and VIL

Vout
V OH

VM

V in
V OL

V IL

V IH

A simplified approach

Gain as a function of VDD

2.5

0.2

0.15

Vout (V)

Vout (V)

1.5

0.1

1
0.05

0.5

0
0

Gain=-1
0.5

Vin (V)

1.5

2.5

0
0

0.05

0.1
Vin (V)

0.15

0.2

Simulated VTC
2.5

Vout (V)

1.5

0.5

0.5

Vin (V)

1.5

2.5

Impact of Process Variations

2.5

Good PMOS
Bad NMOS

Vout(V)

1.5

Nominal
1

Good NMOS
Bad PMOS

0.5

0
0

0.5

Vin (V)

1.5

2.5

Propagation
Delay

CMOS Inverter Propagation Delay

VDD

tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
CL
Ron

ln(0.5)

Vout
1

VDD

0.5
0.36

Vin = V DD
RonCL

CMOS Inverters
VDD
PMOS

1.2m
=2
In

Out
Metal1

Polysilicon

NMOS
GND

Transient Response
3
2.5

tp = 0.69 CL
(Reqn+Reqp)/2

Vout(V)

1.5
1

tpHL

tpLH

0.5
0
-0.5
0

0.5

t (sec)

1.5

2.5

-10

x 10

Design for Performance

Keep capacitances small
Increase transistor sizes
watch out for self-loading!

Increase VDD (????)

Delay as a function of VDD

5.5
5

tp(normalized)

4.5
4
3.5
3
2.5
2
1.5
1
0.8

1.2

1.4

1.6

VDD(V)

1.8

2.2

2.4

Device Sizing
-11

3.8

x 10

(for fixed load)

3.6
3.4

tp(sec)

3.2
3

2.8

Self-loading effect:
Intrinsic capacitances
dominate

2.6
2.4
2.2
2

8
S

10

12

14

NMOS/PMOS ratio
-11

x 10

tpHL

tpLH

tp(sec)

4.5

= Wp/Wn

tp
4

3.5

3
1

1.5

2.5

3.5

4.5

Inverter
Sizing

Inverter Chain
In

Out
CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.

Inverter Delay
Minimum length devices, L=0.25m
Assume that for WP = 2WN =2W
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network
1
1
WP
WN

RP Runit
Runit
RN RW
Wunit
Wunit
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:

tpLH = (ln 2) RPCL

C gin

W
3
Cunit
Wunit

2W

Inverter with Load

Delay

RW

CL
RW

Load (CL)

tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1

Inverter with Load

CP = 2Cunit

Delay

2W
W

CN = Cunit

Cint

CL
Load

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

Example
In
C1

Out
1

f2

CL= 8 C1

CL/C1 has to be evenly distributed across N = 3 stages:

f 38 2

Optimum Number of Stages

For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
C L F Cin f Cin with N
ln f

Buffer Design
1

16

2.8

22.6

tp

64

64

65

64

18

64

15

64

2.8

15.3

Power
Dissipation

Where Does Power Go in CMOS?

Dynamic Power Consumption
Charging and Discharging Capacitors

Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

Leakage
Leaking diodes and transistors

Dynamic Power Dissipation

Vdd

Vin

Vout
CL

Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.

Modification for Circuits with Reduced Swing

Vdd
Vdd
VddVt
CL

E 0 1 = CL Vdd V dd Vt

Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)

Short Circuit Currents

Vdd

Vin

Vout
CL

IVDD (mA)

0.15

0.10

0.05

0.0

1.0

2.0
3.0
Vin (V)

4.0

5.0

How to keep Short-Circuit Currents Low?

Short circuit current goes to zero if tfall >> trise,

but cant do this for cascade logic, so ...

Minimizing Short-Circuit Power

8
7
6

Vdd =3.3

Pnorm

5
4

Vdd =2.5

3
2
1
0

Vdd =1.5
0

tsin/tsout

Leakage
Vdd

Vout

Drain Junction
Leakage
Sub-Threshold
Current

Sub-threshold current one of most compelling issues

Sub-Threshold
in low-energy
circuitCurrent
design!Dominant Factor

Reverse-Biased Diode Leakage

GATE

p+

p+

ReverseLeakageCurrent
+

V
dd

IDL=JSA
2
fora1.2mCMOStechnology
JS = 10-100 pA/m2
at 25 deg C for 0.25m CMOS
JS =15pA/m

JS doubles for every 9 deg C!

Jsdoublewithevery9oCincreaseintemperature

Subthreshold Leakage Component

Static Power Consumption

Vdd

Istat

Vin =5V

Vout

CL

Pstat = P(In=1).Vdd . Istat

Wasted energy

Dominates over dynamic consumption

Should be avoided in almost all cases,
Not a function of switching frequency
but could
help reducing energy in others (e.g. sense amps)

Principles for Power Reduction

Prime choice: Reduce voltage!
Recent years have seen an acceleration in
supply voltage reduction
Design at very low voltages still open question
(0.6 0.9 V by 2010!)

Reduce switching activity

Reduce physical capacitance
Device Sizing: for F=20
fopt(energy)=3.53, fopt(performance)=4.47

Impact of
Technology
Scaling

Goals of Technology Scaling

Make things cheaper:
Want to sell more functions (transistors) per
chip for the same money
Build same products cheaper, sell the same
part for less money
Price of a transistor has to be reduced

But also want to be faster, smaller, lower

power

Technology Scaling
Goals of scaling the dimensions by 30%:
Reduce gate delay by 30% (increase operating
frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency

Die size used to increase by 14% per generation

Technology generation spans 2-3 years

Technology Evolution (2000 data)

International Technology Roadmap for Semicondu

Year of
Introduction

1999

Technology node
[nm]

180

Supply [V]

2000

2001

2004

2008

2011

2014

130

90

60

40

30

0.6-0.9

0.5-0.6

0.3-0.6

9-10

10

3.5-2

7.1-2.5

11-3

14.9
-3.6

1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2

Wiring levels

6-7

6-7

Max frequency
[GHz],Local-Global

1.2

Max P power [W]

90

106

130

160

171

177

186

Bat. power [W]

1.4

1.7

2.0

2.4

2.1

2.3

2.5

1.6-1.4 2.1-1.6

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

Technology Evolution (1999)

Technology Scaling (1)

Minimum Feature Size (micron)

10

10

10

10

-1

-2

10
1960

1970

1980

1990

Year

2000

Minimum Feature Size

2010

Technology Scaling (3)

tp decreases by 13%/year
50% every 5 years!

Propagation Delay

Technology Scaling (4)

1000

10
1
0.1
0.01
80

MPU
DSP
85

Year

(a) Power dissipation vs. year.

90

95

Power Density (mW/mm 2 )

Power Dissipation (W)

100

100

10

1
1

Scaling Factor
normalized by 4 m design rule
(b) Power density vs. scaling factor.
From Kuroda

10

Technology Scaling Models

Full Scaling (Constant Electrical Field)
ideal model dimensions and voltage scale
together by the same factor S

Fixed Voltage Scaling

most common model until recently
only dimensions scale, voltages remain constant

General Scaling
most realistic for todays situation
voltages and dimensions scale with different factors

Scaling Relationships for Long Channel

Devices

Processor Scaling

P.Gelsinger: Processors for the New Millenium, ISSCC 2001

Processor Power

P.Gelsinger: Processors for the New Millenium, ISSCC 2001

Processor Performance

P.Gelsinger: Processors for the New Millenium, ISSCC 2001

2010 Outlook
Performance 2X/16 months
1 TIP (terra instructions/s)
30 GHz clock

Size
No of transistors: 2 Billion
Die: 40*40 mm

Power
10kW!!
Leakage: 1/3 active Power
P.Gelsinger: Processors for the New Millenium, ISSCC 2001

Some interesting questions

What will cause this model to break?
When will it break?
Will the model gradually slow down?
Power and power density
Leakage
Process Variation