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Abstract:
3-D integrated circuits have unique fabrication designs that makes it inexpensive,
compact, and more efficient than planar circuits. The components are integrated
vertically and horizontally using less material.
Outline
Fabrication
Types
Monolithic
Wafer-on-Wafer
Die-on-Wafer
Die-on-Die
Wafer-on-Wafer Steps
Advantages/Disadvantages
Applications
3-D IC Stacked
Problem with stacking is heat dissipation.
Types of Fabrication
Monolithic
Built on single wafer.
Diced into 3-D ICs.
Wafer-on-Wafer
Built on two or more wafers.
Aligned, bonded, and diced into 3-D ICs.
Die-On-Wafer
Components built on two wafers.
One wafer diced and aligned on the second wafer.
Die-On-Die
Components built on multiple dice.
Aligned and bonded into 3-D ICs.
Types of Fabrication
Chip means Die
Fabrication (Wafer-on-Wafer)
Components are built on two or more wafers
Alignment of wafers
Machine checks for alignment mark
Temporarily brought into contact
Inspected for correct alignment
Bonding of wafers
Then bonded together using the method best suited for
that wafer
Such as Direct, Adhesive, or Thermocompression
bonding
Fabrication (Wafer-on-Wafer)
Thinning of wafers
Can be thinned before or after bonding
Dicing Before Grinding
Saws the front before thinning from the
back
Dicing By Thinning
Applies a trench-etching process
Reduces Damage
Fabrication (Wafer-on-Wafer)
Dicing of wafers
Advantages
Chip Performance
Higher Bandwidth
Reduced Power Consumption
Functionality
Circuit Security
Device Packing Density
Fits into a small space
Shorter Interconnects
Cheaper fabrication costs
Disadvantages
Heat due to stacking
Testing methods
Interconnect design
CAD algorithms and tools
Applications
Monolithic IC 3D (Company in California)
Summary
3-D integrated circuits have layered active components that are vertically and
horizontally integrated. With these designs, theres about four different
fabrication types: monolithic, wafer-on-wafer, die-on-wafer, and die-on-die.
These new fabrication designs provide for better chip performance, circuit
security, smaller interconnects, and inexpensive circuits.
References
Pictures:
1. http://esl.epfl.ch/page-42448-en.html
http://domino.research.ibm.com/tchjr/journalindex.nsf/9f
2. http://lsi.epfl.ch/page-13135-en.html
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advances-in-materials-and-processes/low-tem
http://en.wikipedia.org/wiki/Three-dimensional_integrated_circui
perature-wafer-level-metal-thermo-compressi
t
on-bonding-technology-for-3d-integration
4. http://www.tezzaron.com/technology/FaStack
http://homepages.rpi.edu/~luj/Papers/Luj4.pdf
.htm
http://www.wiley-vch.de/publish/dt/books/newTitles201201/3-5
27-32646-4/?sID=p2qlnooj68su7htl8qrrc2qjt3
http://electroiq.com/blog/2003/03/wafer-thinning-techniques-for-u
ltra-thin-wafers/
https://www.coherent.com/Applications/index.cfm?fuseaction
=Forms.page&PageID=273
http://www.monolithic3d.com/applications.html
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