Documente Academic
Documente Profesional
Documente Cultură
sp2016
lec#1
Dr M Shamim Baig
1.1
Course Information
Prereq:
Text/Ref:
Grading Policy
Quizzes
: 10 %
Assignments/Project :
Midterm Exam
:
Final Exam
:
15 %
30 %
45 %
1.2
Course Introduction
With advances in computer architecture, high
performance multiprocessor computers have become
readily available & affordable. As a result, high
performance & supercomputing is accessible to a
large segment of industry that was once restricted to
military research & large corporations. The course is
comprised of architecture, algorithms & programming
of multicore & Parallel computing systems. It focuses
on design concepts, principles, paradigms, models,
performance evaluation and real life applications.
1.3
Parallel Computing
Architectures
Current computer architectures are
increasingly relying upon parallelism to
improve performance:
Pipelined processing
Multiple execution units
Multi-core processor (Cores)
Many-core processor (GPU)
Mutiprocessors (CPUs)&
Multicomputers (PCs/ Workstations)
1.4
Course Contents
Parallel Architecture Models:
Implicit: Pipelining, Superscalar & VLIW.
Explicit: SIMD,MIMD, multicore SMP,
vector/array processor, MPP & Clusters
1.5
Course Contentscontd
Collective Communication Operations:
Broadcast, Reduction, Scatter & Gather
Course Contentscontd
Multicore SMP programming using OpenMP
Message Passing multicomputer/ Cluster
programming using MPI
Massively (data) Parallel Processing (MPP)
using
Course Contentscontd
Parallel Performance Evaluation
Parallel Linpack standard test criteria
Compute/ Communicate Time Analysis
Systems monitoring/ measurement tools
Parallel Performance Laws
Amdhls Law & Gustafsons Law
1.8
Applications of HPC
1.9
1.10
For example:
1.12
1.13
1.14
serial computing
15
1.15
parallel computing
In the simplest sense, parallel computing is the simultaneous
use of multiple compute resources to solve a computational
problem:
To be run using multiple CPUs
A problem is broken into discrete parts that can be solved
concurrently
Each part is further broken down into a series of instructions
Instructions from each part execute simultaneously on
different CPUs
17
1.17