LVS Check

Automation
P. Madhu Sankara Swamy
13VL16F

abstract
Device Libraries and LVS runsets are incremental

design components of Technology Package

Component developers use independent test methods
for checking the specifications
develop a test methodology such that it can be used
to cross check the consistency of LVS runsets in
accordance with the specification
Primary Objective is,
Automation of LVS that checks for all the devices in
the library for LVS correctness and
integration of this methodology into test environment

Two types of Design approaches

Semi-Custom :

In this approach we will use predesigned library

cells for our design
FullCustom :
In this design, a chip is designed from the
scratch to meet a particular need. The emphasis is
on achieving best electrical performance and
minimum area.
The main purpose of the two methods is to simplify
the design process and shorten design cycle time.

Process Design Kit (PDK)

A Process Design Kit is a collection of verified

data files that are used by a set of custom IC

design EDA tools to provide a complete
analog/mixed-signal/RF design flow.
Includes schematic symbols, SPICE models,

Device Libraries, Parameterized Cells(P-Cells),

DRC/LVS runsets, parasitic extraction runsets,
and scripts that run by the EDA tools to
automate the generation and verification of
design data.

PDK (contd..)

Device Libraries
The device library provides following features
Supported category of Devices (e.g. Transistors,

capacitors, resistors, MOSFETs, etc.)

Technology file attached to the devices of library
Power supplies
Symbol and Schematic Views
Layout views
For full custom circuit Design

P Cell (Parameterized
Cell)
A P-Cell is a user defined evaluation procedure

and set of parameter values to drive a desired

implementation of an instance
A P-Cell is a graphic, programmable cell that lets
the designer create a customized instance each
time when it is placed.
Advantages of using P-Cell
Speed up entering layout data by avoiding creation

of duplicate versions
Eliminating errors that can result in maintaining
multiple versions of the same cell
Eliminate the need to explode levels of hierarchy
while changing a small detail of a design

Component Description Format

(CDF)
Describes the parameters and attributes of

individual components
Lets us create and describe our own
components
Checking that values lie within specified ranges
Dynamically changing how parameters are
displayed depending on predefined conditions
Executing a SKILL callback function whenever
certain information changed

CDF Form

Layout Versus Schematic

LVS guarantees a topological match
LVS Check involves three steps
1. Extraction
2. Reduction
3. Comparision

1. Extraction
1. database file contains all the layer information
2. Identifies the device recognition layers, the
terminals, the wiring conductors and via
structures and pins.
2. Reduction
1. Combines extracted components into series
and parallel combinations and generates a
netlist of layout and schematic.
3. Comparision
1. Compares the generated netlists of both
layout and schematic

Adding Pins

set date

Page 12

Variation of Parameters

set date

Page 13

Varying w, n , mfact

Generally LVS checks for

1.
2.
3.
4.
5.

set date

Shorts
Opens
Component Mismatches
Missing Components
Parameter Mismatch

Page 15

Netlist checking of layout & sch. of nch with

diff. params

Page 16

LVS results

Future work
Automization of this LVS check to all the cells

in the library
Integration of this LVS automation check to

the Design flow

Thank you