ERROR

DETECTION
AND
CORRECTION

INTRODUCTION
Data can be corrupted during transmission.
So error detection and correction is
essential for reliable communication.

SINGLE BIT ERROR

Only one bit in the data unit has changed

MULTI BIT ERROR

Two or more bits in the data unit has changed.

BURST ERROR
The length of the burst is measured from the
first corrupted bit to the last corrupted bit.

DETECTION
Error detection uses the concept of redundancy
which means adding extra bits for detecting
errors at the destination.

DETECTION

TYPES OF REDUNDANCY CHECKS

VERTICAL REDUNDANCY CHECK (VRC)

This is also called a parity check.

A parity bit is added to every data unit so
that the total number of 1s becomes even.
Note: some system may use off parity
checking, where the no of 1s should be even.
Limitation: VRC can detect all single bit
errors. It can detect burst errors only if the
total no of errors in each data unit is odd.

VERTICAL REDUNDANCY CHECK (VRC)

LONGITUDINAL REDUNDANCY CHECK (LRC)

In this a block of bits is divided into rows

and a redundant row of bits is added to the
whole block.
Limitation: if two bits in one data unit are
damaged and two bits in exactly the same
positions in another data unit are also
damaged, then LRC checker will not detect
an error.

LONGITUDINAL REDUNDANCY CHECK (LRC)

CHECKSUM GENERATOR

In the sender the checksum generator

subdivided the data unit into equal
segments
All segments are added together using 1s
complement to get the sum
The sum is complemented and becomes the
checksum
The checksum is sent with the data
So if the sum of data unit are T the
checksum will be T.

CHECKSUM CHECKER

The receiver again subdivide the data unit as

checksum generator and adds all and
complements the result.
If the result is zero, the data are accepted ,
otherwise they are rejected.

EXAMPLE:

Data to be sent 10101001 00111001

sum: 11100010 checksum: 00011101
The pattern sent is: 10101001 00111001
00011101
Case 1: suppose receiver receives the same
pattern 10101001 00111001 00011101
Sum : 11111111
complement 00000000 means the pattern
received is error free.

EXAMPLE:

Case 2: suppose there is an error

11101001 00111001 00011101
Sum : 01000000
complement 10111111 means the
received is corrupted.
Case 3: 10101111 11111001 00011101
Sum : 11000110
complement 00111001 means the
received is corrupted.

pattern

pattern

ASSIGNMENT

1. What do you mean by CRC?

2. How CRC checker and ?Generator works?

SINGLE BIT ERROR CORRECTION

Bits have only two states 0 and 1.

To correct the single bit error , the receiver
has to detect the error, locate the location of
the erroneous bit in the received data and
simply reverse the value of the bit.
1. To correct the data we have to first calculate
the no. of redundancy bits (r) required to
correct (m) data bits.
2. As m bits of data are added with r bits of
redundancy bits so the length of code =
m+r.

SINGLE BIT ERROR CORRECTION

3. The equation from which we can determine

no of r bits to correct m bits is as follows:

2r>=m+r+1
If the data bits m=7 then r=4
As

24 >=11

SINGLE BIT ERROR CORRECTION

4. Positioning the redundancy bits

Hamming code is used to do so.
In the example r=4 so these bits are placed in
position 1,2,4,8 (the positions are powers of 2).
We refer these as r1 , r2 , r4, r8

11

10

d d d r8 d d d r4 d r2 r 1
Redundancy bits

SINGLE BIT ERROR CORRECTION

5. Calculating the redundancy bits values

In the hamming code, each r bit is the VRC bit
for one combination of data bits.
The combination used to calculate each of the
four r values for a seven bit data sequence are
as follows:

SINGLE BIT ERROR CORRECTION

5. Calculating the redundancy bits values

1011 1010 1001 1000

0111

0110 0101 0100 0011 0010 0001

r8

r4

r2

r1

11

10

r1 =1 ,3,5,7,9,11
r2 = 2 ,3, 6,7, 10,11
r4 = 4 ,5 ,6,7
r8 = 8,9,10, 11
With these combinations we calculate the r
bits.

For example consider the data bits 1001101

Data
Adding r1
Adding r2
Adding r4
Adding r5

11

10

11

10

11

10

11

10

11

10

Code is 10011100101

1
4

1
4

SINGLE BIT ERROR CORRECTION

6. Error detection and correction

Consider that during transmission the 7th bit
of the code has been changed from 1 to 0.
The receiver takes the transmission and
recalculates 4 new VRCs using the same
combinations as used by the sender.
Then assembles new parity values into a
binary no. in order if r position which gives
the location of the bit in error.

For example consider the data bits 1001101

11

10

11

10

11

10

11

10

The bit in position 7 is in error.

0 1 1 1