UMG8900 Hardware System (SSM256) ISSUE 2.0

UMG8900
Hardware
System(SSM256)
www.huawei.com
Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.
Objectives
Upon completion this course, you will be able to:
Perform UMG8900 shelf frame and boards

classifications, functions and interfaces
Know UMG8900 logical subsystem
Perform the concatenation
Page2
References
UMG8900 System Description
UMG8900 Hardware Description Manual
UMG8900 Architecture and Principle
Page3
Contents
1.
Overview
2.
Board Function
3.
Signaling Flow
4.
Concatenation and Cables
Page4
R4 Networking
Page5
Shelf and Frame
(1) Frame lintel
(2) 9U board
(3) Integrated
fan
(4) 8U board
(5) Filter box
Page6
Shelf and Frame

(1) Frame
(2) Mounting
(3) Embedded fan
lintel
angle
box
(1) Mounting angle
(2) Power-in terminal of frame
(3) Interface for monitoring

cable
(4) Standby power-in terminal of fan

box
(5) Interface for alarm cable
(6) Power-out terminal of fan box
(7) Power-in terminal of fan

box
(8) DIP switch for setting frame ID
Page7
Frame Classification
The main control frame: Manages and controls the whole

UMG8900 equipment and provides clock signals for other frames.
The central switching frame: Implements frame subtending

function.
The service frame : Implements service processing and

interfacing functions.
The extended control frame: It is configured when the networking

with large capacity is required. It is responsible for protocol
processing and connection management, and implements
controlling and managing the service frames.
Page8
Frame Configuration
Power distribution frame
Service frame
#2
Service frame
#5
Extended control frame

#8
Air defence frame
Air defence frame
Air defence frame
Main control frame

#1
Service frame
#4
Service frame
#7
Air defence frame
Air defence frame
Air defence frame
Central switch frame

#0
Service frame
#3
Service frame
#6
Dummy panel
Fiber coiler
Dummy panel
Fiber coiler
Dummy panel
Fiber coiler
Page9
DIP Switch
DIP switch setting

SW4
SW3
SW2
Binary
number
SW1
Frame ID
ON
ON
ON
ON
0000
ON
ON
ON
OFF
0001
ON
ON
OFF
ON
0010
ON
ON
OFF
OFF
0011
ON
OFF
ON
ON
0100
ON
OFF
ON
OFF
0101
ON
OFF
OFF
ON
0110
ON
OFF
OFF
OFF
0111
OFF
ON
ON
ON
1000
Page10
Slot Distribution
Service board
Service board
Service board
Service board
Service board
Service board
O
R
O
R
M
P
U
M
P
U
Service board
O
M
U
Service board
Service board
Service board
Service board
Service board
Service board
Service board
O
M
U
Page11
15
14
13
11 12
8
9 10
7
6
5
4
3
2
1
0
Front boards slot distribution
Slot Distribution
N
E
T
T
N
U
Service board
Service board
T N
N E
U T
Service board
Service board
Service board
Service board
Service board
Service board
10
Service board
11
Service board
13 12
Service board
14
Service board
15
Back boards slot distribution
Page12
Questions
Please describe the classification, function and

location in the shelf of the UMG8900 frames.
How to set the DIP switch?
Please describe the slot distribution of UMG8900.
Page13
Summary
Frame classification, function and distribution in shelf
Slot distribution in frame
Dip switch setting.
Page14
Contents
1.
Overview
2.
Board Function
3.
Signaling Flow
4.
Page15
Contents
2
Board Function
2.1 Hardware System Introduction
2. 2 Operation and Maintenance Subsystem
2.3 Gateway Control Subsystem
2.4 Packet Service Processing Subsystem
2.5 TDM Service Processing Subsystem
2.6 Service Resource Subsystem
2.7 Signaling Forwarding Subsystem
2.8 Clock Subsystem
2.9 Cascading Subsystem
Page16
Hardware System
LMT/iManager
MGC(MSOFTX3000)
O&M Subsystem OMU/MPU Packet

MBus
Switch
PP
U
CMU
Gateway Control
Subsystem
Packet Service Processing Subsystem

ATM
A4L/
A4L/EAC
EAC
IP
E8T/
E8T/E1G
E1G
Service Resource
Subsystem
ASU
ASU
RPU
HRB
NET
VPU
Cascading Subsystem
CLK
Clock Subsystem
SPF
TNU
BLU/FLU
E32/T32
E32/
T32
S2L/S2E
S2L/
S2E
Signaling Forwarding
Subsystem
TDM
TDM Service Processing Subsystem
Page17
Contents
2
Board Function
2.8 Clock Subsystem
Page18
OMU(MOMU)
As the management and control center of the whole
MOMU
equipment, the master and slave MOMUs are inserted in

RUN
ALM
ACT
front slots 7 and 8 in the main control frame.
Providing packet switching function at the control plane

to communicate with all the boards with FE control
interfaces and to exchange information with other
RESET
cascading case.
Embedding a BAM, which provides MML and Telnet

interfaces to configure and maintain boards, and saves
log files and alarm information.
COM0 FE0
frames and manage interfaces in the multi-frame
OFFLINE
HUAWEI
Page19
OMU(MOMU)
Other frame
MPU
(Master)
OMU
(Master)
board
board
OMU
(Slave)
board
board
Main control frame
MPU
(Slave)
board
board
board
board
board
MPU
(Slave)
board
MPU
(Master)
board
board
Board
Other frame
Monitoring and managing the states of all boards in the equipment.

When multiple frames are cascaded, the MOMU monitors and
manages MMPUs in other frames through cascaded control planes.
Implementing state monitoring and power-on/off management on the

equipment through special MBus modules; avoiding attack from
instant currents by controlling board power-on sequence.
Page20
MPU(MMPU)
Implementing control information interaction between

MMPU
the boards and inter-frame control information

interaction as well as interface management in the
RUN
ALM
ACT
case of multiple frames subtended.

Monitoring and managing the status of all boards in
the frame.
RESET
Implementing status querying, monitoring and poweron or power-off management to the equipment
through special maintenance module, and controlling
board power-on sequence to avoid impact from instant
current.
COM0 FE0
OFFLINE
HUAWEI
Page21
Contents
2
Board Function
2.8 Clock Subsystem
Page22
MGW Control Subsystem

MGC(MSOFTX3000)
H.248(FE)
PPU
FE-Switch
CMU
OMU/MPU
Gateway Control
Subsystem
Page23
PPU(MPPB)
Sending manipulation results to the MGC
in the form of H.248 messages.
MPPB
RUN
ALM
Implementing H.248 transcoding, and
FE0
resolving transport-layer and networklayer protocols.

RANAP
SCCP
COM0
H.248
RESET
SCTP/UDP
IP
M3UA
SCTP
IP
OFFLINE
HUAWEI
Stack for Mc interfaceStack for SG function
Page24
CMU(MCMF/MCMB)
HRB
ATM
IP
VPU
TDM
Page25
CMU(MCMF/MCMB)
Providing interfaces to connect with the HRB,

ASU, TNU to control the boards to convert media
streams.
Providing interface to connect with the MPU/OMU

to implement data configuration and output
alarms, debugging information and logs.
MCMF
RUN
ALM
ACT
RESET
It includes two types: CMF (Front board) and CMB

(back board)
OFFLINE
HUAWEI
Page26
MCMB
RUN
ALM
ACT
RESET
COM0
Providing internal interface to connect with the

PPU to implement interaction of H.248 messages.
COM0
OFFLINE
HUAWEI
Contents
2
Board Function
2.8 Clock Subsystem
Page27
Packet Service Processing

Subsystem
CLK/GE/FE
TCU
TCU
VPU
NET
ATM
A4L/
TAC
EAC/
TAC
ASU
ASU
HRU
HRB
Packet service processing

subsystem
OMU/MPU
Page28
E8T/
IP
E8T/
G1O/
G1O/
P1H/P4L
P1H/P4L
ASU(MASU)
Processing ATM services.
MASUb
RUN
ALM
ACT
Providing the standard AAL2/ AAL5

Segmentation and Reassembly (SAR)
function.
Supporting direct forwarding over PVC,

processing functions.
Monitoring and managing the states of

the board and the corresponding back
boards.
Supporting 1+1 backup.
Page29
COM0
OAM cell extraction and luUP interface
OFFLINE
HUAWEI
Back Board Corresponding to

MASU
MA4L
Providing four 155 M singlemode/multi-mode ATM optical

interfaces.
RUN
ALM
ACT
A
4
L
A
4
L
A
S
U
(m)
A
S
U
(s)
Providing the 1+1 backup

function by collaborating with
the service processing board
MASU.
8K_OUT
OFFLINE
HUAWEI
Page30
HRB(MRPU)
Processing IP routes, and converging and distributing

IP services.
Monitoring and managing the states of the board and

the corresponding back boards.
Supporting the Internet Protocols over ATM (IPoA)

function. After the MHRU finishes the adaptation of
the IP data packets to the ATM, the ATM interface
board forwards them on.
Page31
HRB(MRPU)
Processing Internet Protocol (IP) routes, and converging

and distributing IP services.
Monitoring and managing the states of the board and the

corresponding back boards.
Resolving the RTP/Real-time Transport Control Protocol

(RTCP) protocols.
Jitter-buffering RTP services.
Nb UP
RTP/ RTCP
UDP
IP
Page32
Back Board Corresponding to

MRPU
MRPU corresponding back boards include MG1O, MP4L and
ME8T.
Example: MG1O function
Providing one GE interface in conformity with the IEEE8002.3z

standard.
Providing the 1+1 backup function by collaborating with the
service processing board MRPU.
P P
4 4
L L
E E
1 1
G G
G G
1 1
O O
E E
8 8
T T
H H
R R
B B
(m) (s)
H H
R R
B B
(m) (s)
H H
R R
B B
(m) (s)
H H
R R
B B
(m) (s)
Page33
NET(MNET)
to exchange service data between all packet service boards in
the frame.
Cascading two frames instead of cascading boards. The

embedded cascading module in the MNET enables
interworking of 2 GE service data planes and interworking
of 2 FE service control planes.
RUN
ALM
ACT
Providing service control and maintenance interfaces for the

corresponding front boards such as the MOMU and MMPU to
address back cabling requirements.
MNET
CLK1_IN CLK0_IN FE1 FE0 MIR OMC
Providing packet service switching channels in its own frame
OFFLINE
Receiving clock signals from the MCLK, and sending them to

TDM service processing boards after phase lock, signal driving
and distributing.
COM0
Page34
HUAWEI
NET(MNET)
The internal clocks synthesized and distributed by the MNET

are as follows:
32.768 MHz clock: the TDM HW synchronous clock signals for

the TDM bearer processing
38.88 MHz clock: the TDM SDH synchronous clock, including
the synchronous clock required by the ATM and POS services in
the SDH transmission mode
77.76MHz clock: the clock signal for the SDH 155 MHz line
interface
2 kHz clock: the TDM SDH frame clock
The TNU, E32, T32, S2L, S1L, TCU, BLU, SPF and ECU use
32.768 MHz, 38.88 MHz and 2 kHz clock signals. Besides the
three clock signals, S1L and S2L use 77.76 MHz signal. The
A4L and P1H only use the 38.88 MHz clock signal.
Page35
Contents
2
Board Function
2.8 Clock Subsystem
Page36
TDM Service Processing

Subsystem
TDM service processing
subsystem
TDM
4*TDM
Packet processing
subsystem
TNU
E32/T32/
E32/T32/
S2L/S2E
S2L/S2E
VPU
VPU
VPU
OMU/MPU
Page37
TNU(MTNB)
Establishing and releasing TDM timeslots in
MTNB
cooperation with TDM service interface boards, and

providing 8 K or 1 K switching capacity for each
RUN
ALM
ACT
interface board.
Connecting with the MTNB of another frame directly

or through the UG02MBLU by multi-mode optical
fibers, and providing 32 K timeslot cascading
Managing and maintaining the boards through the

specified MBus module. Reporting the status and
version of the boards to the main control board of
the local frame. Communicating with the main
control board of the local frame through the FE
interface.
Page38
COM0
capacity.
OFFLINE
HUAWEI
S2L(MS2L)
MS2L
Extracting clock signals and forming

frames at the two 155 M optical
RUN
ALM
ACT
interfaces.
Processing overheads of regenerator
8K_OUT
section and multiplex section of optical

signals and checking communication over
COM0
optical channels.
OFFLINE
Implementing SDH mapping, de-mapping

and processing overheads of high-order
HUAWEI
path and low-order path.
Forming 2 63 E1
Page39
E32(ME32)
Providing 32 E1 interfaces.
Providing 32 E1 frames.
Providing the function of drawing the line
ME32
signaling of the R2 signaling or inserting the
E1/T1_16-31 8K_OUT
E1/T1_0-15
RUN
ALM
signaling.
Providing 8 kHz line clock reference source for

the master and slave MCLKs by distributing
cables at the board panel.
Receiving SSM information from the E1

interface and sending it to the clock system.
OFFLINE
HUAWEI
Providing service link loopback at all levels and

service channel detection within the board.
Page40
Contents
2
Board Function
2.8 Clock Subsystem
Page41
VPU(MVPB)
Supporting functions such as announcement playing, digit

collecting, audio mixing and Multiple Frequency Control
(MFC).
Implementing IP packet adaptation of voice services

based on UDP, Real-time Transport Protocol (RTP), and IP.
Supporting varied voice codec types including G.711A,
G.711, G.723, G.726, G.729, AMR, AMR 2 and FR/HR/EFR.
Accepting resource control and management from the

CMU..
Page42
VPU(MTCB)
Supporting announcement playing, digit collecting, audio mixing and

MFC.
Implementing IP packet adaptation of voice services based on UDP,

RTP and IP. Supporting varied voice codec types including G.711A,
G.711, G.723, G.726, G.729, AMR, AMR 2 and FR/HR/EFR.
Processing IuUP and NbUP at the same time and being fully in line with
the 3GPP TS 25.415 TS 29.415 protocol.
Providing the EC function, supporting 32 ms, 64 ms and 128 ms tail

delay, being in line with the G.168-2000 standard and supporting
G.164/165 tone detection.
Receiving the resource control and management of the CMU.
Page43
Contents
2
Board Function
2.8 Clock Subsystem
Page44
SPF(MSPF)
Implementing signaling gateway functions. The pinch boards that

attached on the MSPF, receives signaling from TDM switching boards and
then deals with it at TDM level, and then the MSPF adapts TDM signaling
to IP packets.
Implementing the core function of a signaling gateway by

M3UA//M2UA/V5UA/IUA adaptation on signaling, and forwarding adapted
messages to the MGC.
SEP
SS7
UMG8900
IP
S7UP
S7UP
MTP3
MTP2
MTP1
MSOFTX3000
TDM
M2UA-NIF
M2UA
MTP2
SCTP
IP
MTP1
MAC
MTP3
IP
M2UA
SCTP
IP
MAC
Page45
Contents
2
Board Function
2.8 Clock Subsystem
Page46
Clock Subsystem
Page47
CLK(MCLK)
CLK is the system clock board, responsible for receiving
line clock signals extracted by interface boards and
external synchronous clock signals provided by BITS.
Each MGW frame is configured with two NET boards. In

the main control frame, the clock boards provide 16-kHz
clock signals to the NET boards of the frame through the
backplane. In other MGW frames, the clock boards
provide 16-kHz clock signals to the NET boards through
the distributed cables.
The CLK also outputs external synchronous clock signals.
MCLK
RUN
ALM
ACT
8K_IN2 8K_IN1
2M_IN 2M_OUT CLK_OUT2 ANT CLK_OUT1 CLK_OUT0
OFFLINE
HUAWEI
Page48
Contents
2
Board Function
2.8 Clock Subsystem
Page49
Cascading Subsystem
1#
0#
B
L
U
2#
B
L
U
B
L
U
B
L
U
B
L
U
3#
B
L
U
T
N
U
N
E
T
N
E
T
T
N
U
T
N
U
N
E
T
N
E
T
T
N
U
4#
4*8K TDM
B
L
U
5#
N
E
T
8#
B
L
U
B
L
U
B
L
U
6#
B
L
U
B
L
U
7#
N
E
T
2*GE
1*FE
Page50
BLU(MBLU)
Providing 4x8 K TDM narrowband data channels to directly
connect frames through multi-mode optical fibers that are
RUN
ALM
ACT
no more than 50 m spaced.
MBLUb
Providing 2x1.25 G broadband packet data channels to
FE0
GE
directly connect frames through multi-mode optical fibers

that are no more than 50 m spaced.
TDM
Providing 1x100 M IP control data channels to directly

connect frames through category-5 twisted pair or super
spaced.
Providing board management and maintenance by the

dedicated MBus module of the board, communicating with
and reporting board status and version to the main control
board through FE channels.
Page51
COM0
category-5 twisted pair that are no more than 50 m
OFFLINE
HUAWEI
FLU(MFLU)
Providing 1x8 K TDM data cascading channel for the

MBLU.
Providing 1x1.25 G IP data cascading channel for the

MBLU.
Providing 2x8 K TDM data cascading channels and 2x1.25

G GE data cascading channels for the MBLU by two MFLU
boards in load-sharing mode.
Interacting with the main control board through a

dedicated maintenance module to monitor board
temperature, voltage and control power-on/off.
Page52
Questions
Please describe the UMG8900s boards

classifications and each classs function
Page53
Summary
UMG8900s logical subsystem
UMG8900s boards classification and each function
Page54
Contents
1.
Overview
2.
Board Function
3.
Signaling Flow
4.
Page55
Contents
3
Signaling Flow
3.1 Service Signaling Flow
3.2 Clock Signaling Flow
3.3 Loading Signaling Flow
3.4 Alarm Signaling Flow
Page56
Service Signaling Flow
Gateway Signal Control Flow (IP bearer)
Page57
Transfer flow for the UMTS access network signaling

(PPU adaptation)
MSOFTX3000
RNC
Page58
Transfer flow for the UMTS access network signaling

(SPF adaptation)
MSOFTX3000
RNC
Page59
SS7 transfer flow

BSC
MSOFTX3000
Page60
Bearer Data Flow (TDMIP)

TDM
Back
E
3
2
IP
N
E
T
T
N
U
E
8
T
Front
GE
TDM
V
P
U
H
R
B
Page61
Bearer Data Flow

(TDMATM)
ATM
TDM
Back
E
3
2
N
E
T
T
N
U
A
4
L
Front
GE
TDM
V
P
U
A
S
U
Page62
Bearer Data Flow (ATMIP)

ATM
IP
Page63
Bearer Data Flow (IPIP)

IP (Domain 0)
IP (Domain 1)
Page64
Service Resource Signal Flows
Announcement Playing Signal Flow
Page65
Contents
3
Signaling Flow
Page66
Clock Extraction
BITS
GPS/GLONASS
1.5GHz 1.5GHz
2048kbit/s
2048KHz
M
C
L
K
M
C
L
K
M
N
E
T
M
N
E
T
M
E
3
2
M
E
3
2
Main
Control
Frame
8KHz
Page67
Clock Distribution
Page68
Contents
3
Signaling Flow
Page69
FTP Server
LMT
FE crossover
network cable
C
L
K
A
4
L
T
N
U
N
E
T
N
E
T
T
N
U
P
4
L
E
8
T
G
1
O
S
2
L
E
3
2
master/ slave
FE control bus
V
P
U
A
S
U
FE crossover
network cable
FTP service
O
M
U
O
M
U
H
R
U
RS232 cable
hyper terminal
Page70
OMU Embedded BAM

O
M
U
T
N
U
N
E
T
O
M
U
main control
frame
master/slave
FE bus
N
E
T
T
N
U
N
E
T
T
N
U
1*FE
N
E
T
M
P
U
M
P
U
service
F
L
U
T
N
U
board
B
L
U
central exchange
frame
master/slave
FE bus
Page71
OMU Embedded BAM

O
O
M
M
U
U
main control frame
master/slave
FE bus
T
T
N
N E NE N
U T T U
central exchange frame
M M
P P
U U
F
L
U
B
L
U
T
N
U
N
E
T
N
E
T
F
L
U master/slave
FE bus
T
N
U
B
L
U
1*FE+2*GE+4*TDM
T
T
N N N N
E E
U T T U
service frame
M M
P P
U U
master/slave
FE bus
extended control frame
T
N
U
NN NN
EE EE
TT TT
M
M M
M
PP PP
UU UU
T
N master/
U slave
FE bus
service
board
M M
P P
U U
master/slave
FE bus
T N N T
N E E N
U T T U
service frame
Page72
Contents
3
Signaling Flow
Page73
Alarm Path
LMT
Note: when LMT is connected
with the host through LanSwitch,
the straight-thru cable is used
crossover network
cable
service
board
C
L
K
A
4
L
M
T
N
U
N
E
T
N
E
T
T
N
U
P
4
L
M
S
2
L
M
E
3
2
master/ slave
master/ slave
A
S
U
O
M
U
O
M
U
H
R
U
V
P
U
service
board
V
P
U
FE bus
Mbus
Page74
Alarm Path
T
N
U
O
M
U
O
M
U
N
E
T
N
E
T
main control frame

master/
slave
FE bus
T
N
U
1*FE+2*GE+4*TDM
F
L
U
T
N
U
N
E
T
N
E
T
M
P
U
M
P
U
T
N
U
service
board
B
L
U
central exchange frame
master/
slave
Mbus bus
R
P
U
Page75
Alarm Path
main control frame

O O
M M master/slave
U U
FE bus
T
T
N N N N
U E E U
T T
F
L
U
M M
P P
U U
F
L
U maste
r/slave
FE bus
central
exchange
frame
B T N N T B
L N E E N L
U U T T U U
1*FE+2*GE+4*TDM
T
T
N N
N N
E
U E
T T U
service frame
M M
P P
U U
extended control frame
T
T
N N N N
U E E U master/
T T
slave
Mbus
M M
P P
U U
sevice
board
M M
P P
U U
master/
slave
Mbus
T
T
N N
N N
E
U E
T T U master/
slave
Mbus
service frame
Page76
Questions
Please describe all kinds of signaling flow.
Page77
Summary
Service signaling flow
Clock signaling flow
Loading signaling flow
Alarm signaling flow
Page78
Contents
1.
Overview
2.
Board Function
3.
Signaling Flow
4.
Page79
Contents
4

4.1 Cascading Cable Distribution
4.2 Clock Cable Distribution
4.3 Monitoring Cable Distribution
Page80
Two Frames Cascading
1#
T
N
U
N
E
T
N
E
T
T
N
U
2#
T
N
U
N
E
T
N
E
T
T
N
U
4*8K TDM
2*GE
1*FE
Page81
More than Three Frames

Cascading
1#
0#
B
L
U
2#
B
L
U
B
L
U
B
L
U
B
L
U
3#
B
L
U
T
N
U
N
E
T
N
E
T
T
N
U
T
N
U
N
E
T
N
E
T
T
N
U
4#
4*8K TDM
B
L
U
5#
N
E
T
8#
B
L
U
B
L
U
B
L
U
6#
B
L
U
B
L
U
7#
N
E
T
2*GE
1*FE
Page82
Contents
4

Page83
Clock Extraction
Page84
Clock Cable Distribution
Page85
Contents
4

Page86
Monitoring Cable Distribution

Power distribution frame DB15
Service frame
Power distribution frame DB15
Service frame
DB9
Fan box
DB15
Air deflector
DB9
Fan box
Air deflector
Main control frame
Service frame
DB9
Fan box
DB15
DB9
Fan box
Air deflector
Air deflector
Central switch frame
Service frame
DB9
Fan box
DB15
DB15
Main control cabinet
DB15
DB9
Fan box
DB15
Service cabinet
Page87
Questions
If there are 4 frames, how to cascade them?
Page88
Summary
Cascading cable distribution
Clock cable distribution
Monitoring cable distribution
Page89
Summary
Board functions
Signaling flow
Concatenation and cables
Page90
Thank you
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UMG8900 Hardware System (SSM256) ISSUE 2.0

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UMG8900 Hardware System (SSM256) ISSUE 2.0

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UMG8900

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Upon completion this course, you will be able to:

Perform UMG8900 shelf frame and boards

Know UMG8900 logical subsystem

Perform the concatenation

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

UMG8900 System Description

UMG8900 Hardware Description Manual

UMG8900 Architecture and Principle

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Concatenation and Cables

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Shelf and Frame

(1) Frame lintel

(5) Filter box

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Shelf and Frame

(3) Embedded fan

(1) Mounting angle

(2) Power-in terminal of frame

(3) Interface for monitoring

(4) Standby power-in terminal of fan

(5) Interface for alarm cable

(6) Power-out terminal of fan box

(7) Power-in terminal of fan

(8) DIP switch for setting frame ID

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

The main control frame: Manages and controls the whole

The central switching frame: Implements frame subtending

The service frame : Implements service processing and

The extended control frame: It is configured when the networking

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Power distribution frame

Power distribution frame

Extended control frame

Air defence frame

Air defence frame

Air defence frame

Main control frame

Air defence frame

Air defence frame

Air defence frame

Central switch frame

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

DIP switch setting

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Front boards slot distribution

Back boards slot distribution

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Please describe the classification, function and

How to set the DIP switch?

Please describe the slot distribution of UMG8900.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Frame classification, function and distribution in shelf

Slot distribution in frame

Dip switch setting.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Concatenation and Cables

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

O&M Subsystem OMU/MPU Packet