Simple As Possible -1 (SAP-1)

Computer Architecture
2004

SAP-1 Characteristics

Hardwire Architecture
2 8-bit general registers
1 8-bit output registers
4-bit ALU (additional, subtraction)
4-bit instructions and 4-bits operands
(cccc oooo)
cccc = OP CODE
oooo = OPERAND

16x8 address ROM for mixed program and data

12 control signals

SAP-1
Architecture

D[0..3]

Program Counter
U1
D0
D1
D2
D3
CLK

UCLK
DCLK
CNTUP

Ep
Cp

OE
CE
LOAD
RE SET

CLR

COUNTE R_4

Q0
Q1
Q2
Q3
MIN
MAX
RCO

D0
D1
D2
D3

OUTPUT: 0000-1111 (0-F)

CLK: Clock cycle
CLR: reset output to 0000
Cp: (PC) (PC)+1
Ep: output (PC)

Q[0..3]

D[0..3]

MAR
U2
D0
D1
D2
D3

CLK

Lm

DL
D0
D1
D2
D3

QL
Q0
Q1
Q2
Q3

DU

QU

CLK
RESET
HOLD
UP
LOAD
OE
SHIFT REG_4

INPUT: 8 bits (cccc oooo)

OUTPUT: 4 bits (cccc)
CLK: Clock cycle
Lm:
(MAR) input
output HiByte(MAR)

D[0..7]

A[0..3]

ROM (R)
U3
A0
A1
A2
A3

Vcc

Er

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

D0
D1
D2
D3
D4
D5
D6
D7

CS
WR
RD
MEMORY_12_8
FILE=PROM.BIN,ASCHEX

D0
D1
D2
D3
D4
D5
D6
D7

INPUT: 4 bits (cccc)

OUTPUT: 8 bits (dddd dddd)
Er:
R input
output (R)

B,O Register (tri-state)

U51
X[0..7]

D[0..7]
DL
D0
D1
D2
D3
D4
D5
D6
D7
DU

CLK
CLR

Li
Ei

Q[0..7]
QL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
QU

CLK
RESET
HOLD
UP
L OAD
OE
SHIFT REG_8_BUS

Y[0..7]

INPUT: 8 bits (dddd dddd)

OUTPUT: 8 bits (dddd dddd)
CLK: Clock cycle
Lx: Load data in
(A) input
Ex: Enable data out
output (A)

I Register

INPUT: 8 bits
OUTPUT1: 8 bits

OUTPUT2: 8 bits

For ALU, direct output

For BUS, control by Ea

CLK: Clock cycle

La: Load data in
(A) input
Ea: Enable data out
output2 (A)

INPUT: 8 bits (cccc dddd)

OUTPUT1: 4 bits (cccc)

OUTPUT2: 4 bits (dddd)

For instruction decoder, direct output

For BUS, control by Ei

CLK: Clock cycle

Li: Load data in
(IR) input
Ei: Enable data out
output2 (IR)

ALU

INPUT1: 8 bits (aaaa aaaa)

INPUT2: 8 bits (bbbb bbbb)
OUTPUT: 8 bits (dddd dddd)
Su: Load data in
0 additional

1 subtraction

(ALU)input1+input2
(ALU)input1-input2

Eu: Enable data out

output (ALU)

Binary Display

INPUT: 8 bits (aaaa aaaa)

Control Unit (CON)

RC
CLK
CLR

CLK
CLR

I[4 . . 7 ]

T[0..5]
RINGCOUNTER

ID
I7
I6
I5
I4

CM
I7
I6
I5
I4

LDA
ADD
SUB
OUT
HLT

LDA
ADD
SUB
OUT

INSTRUCTION DECODER

T[0..5]

Lo
Lb
Eu
Su

Lo
Lb
Eu
Su

Ea
La
Ei
Li

Ea
La
Ei
Li

Er
Lm
Ep
Cp

Er
Lm
Ep
Cp

CONTROL MATRIX
HLT

COMPONENTS

Ring Counter

Instruction Decoder

T0 T5
6 op-code signals

Control Matrix

12 control signals

CLOCK

Press START to begin

Generate CLK
Generate CLR

HLT Signal

Reset system to Initial state

CLOCK(CLK1)

Vcc

U101
CLK1
CLK
AND

START

U19

CLOCK
CLK1
CLK
START1 CLR

START1
START2

JKFF
HLT
CLR1

START2

CLR1

CLK
CLR

HLT

CLOCK GENERATOR

J
K
SET
RESET
CLK

U20
Q
!Q

J
K
SET
RESET
CLK
JKFF

Q
!Q

CLR

OPCODE

0000 1001 = LDA (R9)

(A) (R9)

ADD (1111 oooo)

0001 1010 = ADD (RA)
(B) (RA)
(A) (A)+(B)

SUB (0010 oooo)

0010 1100 = SUB (RC)
(B) (RC)
(A) (A) (B)

OUT (1100 xxxx)

1100 xxxx = OUT
(D) <- (A)

PROGRAM/DATA MEMORY

LDA (0000 oooo)

HLT (1111 xxxx)

1111 xxxx = HLT

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
RC
RD
RE
RF

0000
0001
0001
0001
0010
1110
1111
xxxx
xxxx
0001
0001
0001
0001
0010
xxxx
xxxx

1001
1010
1011
1100
1101
xxxx
xxxx
xxxx
xxxx
0000
0100
1000
1100
0000
xxxx
xxxx

(LDA
(ADD
(ADD
(ADD
(SUB
(ADD
(ADD
(16)
(20)
(24)
(28)
(32)

R9)
RA)
RB)
RC)
RD)
RA)
RA)

Ring Counter

RC
CLK
CLR

CLK
CLR

T[0..5]
RINGCOUNTER

Machine Cycle

Fetch Cycle (T0-T2)

Execute Cycle (T3-T5)

Fetch Cycle
T0
EpLm CON
(MAR) (PC)

T1
ErLi CON
(IR) (RMAR)

T2
Cp CON
(PC) (PC)+1

Execute Cycle
LDA

ADD

T3

T3

LmEi CON
(MAR) (oooo)

T4
ErLa CON
(A) (Roooo)

T5
No op

LmEi CON
(MAR) (oooo)

T4
ErLb CON
(B) (Roooo)

T5
LaEu CON
(ALU) (A)+(B)
(A) (ALU)

Execute Cycle
SUB

OUT

T3

T3

LmEi CON
(MAR) (oooo)

T4
ErLb CON
(B) (Roooo)

T5
LaSuEu CON
(ALU) (A)+(B)
(A) (ALU)

EaLo CON
(O) (A)

T4
No Op

T5
No Op

HLT
T3
HLT signal

CONTROL UNIT (CON)

Instruction Decoder
I7

I6

I5

I4

U4

U5

U6

U7

N OT

NOT

NOT

N OT

U8
LDA
AN D_4

U9
AD D
AN D_4

U10
SU B
AN D_4

U11
OU T
AN D_4

U12
HLT
AN D_4

CONTROL MATRIX
T0
T1
T2
T3
T4
T5

T[0.5]

LDA
ADD
SUB
OUT

U29 U30 U31

U33 U34

U36 U37

AND

AND

AND AND

AND

AND

AND

AND

U41

U42

U43

U44

U45

OR_4

OR_3

OR_3

OR

OR

S u
E u
L b
L d

C p
E p
L m
E r

OR_4

U26 U27
AND

AND

L i
E i
L a
E a

U40

U23 U24
AND

Operation sample
PROGRAM/DATA MEMORY

Press start button

(PC) 0000
Start
LDA R9
(MAR) (PC)
R(MAR) 0000 1001
IR 0000 1001
(PC) (PC)+1
(MAR) IR(low)
(A) R(MAR)
NOOP
ADD RA
(MAR) (PC)
R(MAR) 0001 1010
IR 0001 1010
(PC) (PC)+1
(MAR) IR(low)
(B) R(MAR)
(A) (A)+(B)
ADD RB
.
.
.

fetch TO
fetch T1
fetch T2
exec T3
exec T4
exec T5
fetch TO
fetch T1
fetch T2
exec T3
exec T4
exec T5

(MAR)= 0000
(R) = (R0)
(PC) = 0001
(MAR)= 1001
(A) = (R9)

(MAR)= 0001
(R)= (R1)
(PC) = 0010
(MAR)= 1010
(B)= (RA)
(A)= 16+20

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
RC
RD
RE
RF

0000
0001
0001
0001
0010
1110
1111
xxxx
xxxx
0001
0001
0001
0001
0010
xxxx
xxxx

1001
1010
1011
1100
1101
xxxx
xxxx
xxxx
xxxx
0000
0100
1000
1100
0000
xxxx
xxxx

(LDA
(ADD
(ADD
(ADD
(SUB
(ADD
(ADD
(16)
(20)
(24)
(28)
(32)

R9)
RA)
RB)
RC)
RD)
RA)
RA)