Digital Integrated Circuits

Digital Integrated
Circuits
Jan M. Rabaey
AAnantha
Design
Perspective
Chandrakasan
Borivoje Nikoli
Designing Combinational
Logic Circuits
November 2002.
EE141 Integrated Circuits
Digital
2nd
Combinational Circuits
Combinational vs. Sequential Logic
In
Combinational
Logic
Circuit
In
Out
Out
Combinational
Logic
Circuit
State
Combinational
Output = f(In)
Digital
2nd
Sequential
Output = f(In, Previous In)
2
Static CMOS Circuit

At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

Digital
2nd
Static Complementary CMOS

VDD
In1
In2
PUN
InN
F(In1,In2,InN)
In1
In2
InN
PMOS only
PDN
NMOS only
PUN and PDN are dual logic networks

Digital
2nd
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A
Y = X if A and B
Y = X if A OR B
NMOS Transistors pass a strong 0 but a weak 1

Digital
2nd
PMOS Transistors
PMOS switch closes
when switch control input is low
in Series/Parallel
Connection
A
Y = X if A AND B = A + B
Y = X if A OR B = AB
PMOS Transistors pass a strong 1 but a weak 0

Digital
2nd
Threshold Drops
VDD
PUN
VDD
VDD
0 VDD
VGS
CL
VDD 0
PDN
VDD

Digital
2nd
CL
0 VDD - VTn
CL
VGS
VDD |VTp|
S
CL
D
7
Complementary CMOS Logic Style

Digital
2nd
Example Gate: NAND

Digital
2nd
Example Gate: NOR

Digital
2nd
10
Complex CMOS Gate

B
A
C
D
OUT = D + A (B + C)
A
D
B

Digital
2nd
11
Constructing a Complex Gate

VDD
VDD
C
SN4
SN1
F
A
SN3
D
B
SN2
F
(a) pull-down network
(b) Deriving the pull-up network

hierarchically by identifying
sub-nets
A
D
B
(c) complete gate

Digital
2nd
12
Cell Design
Standard
Cells
General purpose logic

Can be synthesized
Same height, varying width
Datapath
Cells
For regular, structured designs (arithmetic)

Includes some wiring in the cell
Fixed height and width
Digital
2nd
13
Standard Cell Layout Methodology

1980s
Routing
channel
VDD
signals
GND

Digital
2nd
14
Standard Cell Layout Methodology

1990s
Mirrored Cell
No Routing
channels
VDD
VDD
M2
M3
GND
Mirrored Cell

Digital
2nd
GND
15
Standard Cells
N Well
VDD
Cell height 12 metal tracks

Metal track is approx. 3 + 3
Pitch =
repetitive distance between objec
Cell height is 12 pitch
In
GND
Cell boundary

Digital
Out
2nd
Rails ~10
16
Standard Cells
VDD
With minimal
diffusion
routing
VDD
With silicided
diffusion
VDD
M2
In
In
Out
Out
In
Out
M1
GND

Digital
2nd
GND
17
Standard Cells
VDD
2-input NAND gate

VDD
Out
GND

Digital
2nd
18
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD
VDD
Inverter
NAND2
Out
Out
In
GND

Digital
GND
2nd
A B
19
Stick Diagrams
Logic Graph
A
j
B
X = C (A + B)
C
VDD
j
B
A
B
C

Digital
X
B
2nd
PUN
GND
A
PDN
20
Two Versions of C (A + B)
A
VDD
VDD
X
GND

Digital
GND
2nd
21
Consistent Euler Path

X
C
i
X
B
VDD
j
GND

Digital
2nd
A
A B C
22
OAI22 Logic Graph

A
X
D
X = (A+B)(C+D)
C

Digital
2nd
C
VDD
X
B
A
B
C
D
PUN
A
GND
PDN
23
Example: x = ab+cd
x
x
c
VDD
x
a
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}

VD D
x
GND
a
(c) stick diagram for ordering {a b c d}

Digital
2nd
24
Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance

Digital
2nd
25
Properties of Complementary CMOS Gates

Snapshot
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)

Digital
2nd
26
CMOS Properties
Full rail-to-rail swing; high noise margins
Logic levels not dependent upon the relative
device sizes; ratioless
Always a path to Vdd or Gnd in steady state; low
output impedance
Extremely high input resistance; nearly zero
steady-state input current
No direct path steady state between power and
ground; no static power dissipation
Propagation delay function of load capacitance
and resistance of transistors

Digital
2nd
27
Switch Delay Model

Req
A
A
Rp
A
Rp
Rp
B
Rn
Rp
CL
A
Cint
A
INV
NAND2
Digital
2nd
Rp
A
Rn
B
Rn
B
Cint
A
CL
Rn
Rn
CL
NOR2
28
Input Pattern Effects on Delay

Delay is dependent on
the pattern of inputs
Low to high transition
Rp
A
Rp
B
Rn
both inputs go low
CL
delay is 0.69 Rp/2 CL
B
Rn
A
one input goes low

Cint
delay is 0.69 Rp CL
High to low transition

both inputs go high
delay is 0.69 2Rn CL

Digital
2nd
29
Delay Dependence on Input Patterns

3
Input Data
Pattern
Delay
(psec)
A=B=01
67
A=1, B=01
64
A= 01, B=1
61
0.5
A=B=10
45
A=1, B=10
80
A= 10, B=1
81
A=B=10
2.5
Voltage [V]
A=1 0, B=1
1.5
A=1, B=10
-0.5
100
200
time [ps]
EE141 Integrated Circuits2nd
Digital
300
400
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
30
Transistor Sizing
Rp
2 A
Rp
B
Rn
2
Rn
4 B
2
CL
Cint

Digital
Rp
2nd
Rp
Cint
Rn
Rn
CL
1
31
Transistor Sizing a Complex

CMOS Gate
A
8 6
8 6
4 3
4 6
OUT = D + A (B + C)
A
1
B

Digital
2nd
2C
32
Fan-In Considerations
A
CL
C3
C2
C1

Digital
2nd
Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates
rapidly as a function of fan-in
quadratically in the worst case.
33
tp as a Function of Fan-In
1250
quadratic
tp (psec)
1000
Gates with a
fan-in
greater than
4 should be
avoided.
750
tpHL
500
tp
250
tpLH
linear
0
2
10
12
14
16
fan-in

Digital
2nd
34
tp as a Function of Fan-Out
tpNOR2
tpNAND2
tpINV
tp (psec)
2
All gates
have the
same drive
current.
10
12
14
16
Slope is a
function of
driving
strength
eff. fan-out
Digital
2nd
35
tp as a Function of Fan-In and Fan-Out

Fan-in:
quadratic due to increasing

resistance and capacitance
Fan-out: each additional fan-out gate
adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO

Digital
2nd
36
Fast Complex Gates:

Design
Technique
1
Transistor
sizing
as long as fan-out capacitance dominates
Progressive
InN
sizing
CL
MN
In3
M3
C3
In2
M2
C2
In1
M1
C1

Digital
2nd
Distributed RC line
M1 > M2 > M3 > > MN
(the fet closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
37
Fast Complex Gates:

Design
Technique
2
Transistor
ordering
critical path
charged
CL
In3 1 M3
In2 1 M2
C2 charged
In1
M1
01
C1 charged
delay determined by time to

discharge CL, C1 and C2
Digital
2nd
critical path
01
In1
M3
CLcharged
In2 1 M2
C2 discharged
In3 1 M1
C1 discharged
delay determined by time to

discharge CL
38
Fast Complex Gates:

Technique
3
Design
Alternative
logic structures
F = ABCDEFGH

Digital
2nd
39
Fast Complex Gates:

Design
Technique
4
Isolating fan-in from fan-out using buffer
insertion
CL

Digital
2nd
CL
40
Fast Complex Gates:

Design
Technique 5
Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
linear reduction in delay

also reduces power consumption
But the following gate is much slower!

Or requires use of sense amplifiers on the
receiving end to restore the signal level (memory
design)

Digital
2nd
41
Sizing Logic Paths for Speed

Frequently, input capacitance of a logic path is
constrained
Logic also has to drive some capacitance
Example: ALU load in an Intels microprocessor
is 0.5pF
How do we size the ALU datapath to achieve
maximum speed?
We have already solved this for the inverter
chain can we generalize it for any type of
logic?

Digital
2nd
42
Buffer Example
In
Out
1
CL
Delay pi g i f i
i 1
(in units of inv)
For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?
Digital
2nd
43
Logical Effort
CL
Delay k Runit Cunit 1

Cin
p g f
p intrinsic delay (3kRunitCunit) - gate parameter f(W)
g logical effort (kRunitCunit) gate parameter f(W)
f effective fanout
Normalize everything to an inverter:
ginv =1, pinv = 1
Divide everything by inv
(everything is measured in unit delays inv)
Assume = 1.
EE141 Integrated Circuits2nd
Digital
44
Delay in a Logic Gate

Gate delay:
d=h+p
effort delay
intrinsic delay
Effort delay:
h=gf
logical
effort
effective fanout =
Cout/Cin
Logical effort is a function of topology, independent of sizing

Effective fanout (electrical effort) is a function of load/gate size
Digital
2nd
45
Logical Effort
Inverter has the smallest logical effort and
intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitance
when sized to deliver the same current
Logical effort increases with the gate
complexity

Digital
2nd
46
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
VDD
VDD
F
A
VDD
1
A
B
Inverter
g = 4/3

Digital
2nd
2-input NAND
g=1
2-input NOR
g = 5/3
47
Normalized delay (d)
Logical Effort of Gates

t pNAND
g=
p=
d=
t pINV
g=
p=
d=
F(Fan-in)
1

Digital
2nd
3
4
5
Fan-out (h)
48
Normalized delay (d)

t pNAND
g = 4/3
p=2
d = (4/3)h+2
t pINV
g=1
p=1
d = h+1
F(Fan-in)
1

Digital
2nd
3
4
5
Fan-out (h)
49
Normalized Delay
5
4
3
Effort
Delay
2
1
Intrinsic
Delay
1

Digital
2nd
3
Fanoutf
5
50
Add Branching Effort

Branching effort:
b

Digital
2nd
Con path Coff path

Con path
51
Multistage Networks
N
Delay pi g i f i
i 1
Stage effort: hi = gifi

Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2gN
Branching effort: B = b1b2bN
Path effort: H = GFB
Path delay D = di = pi + hi
Digital
2nd
52
Optimum Effort per Stage

When each stage bears the same effort:
hN H
hN H
Stage efforts: g1f1 = g2f2 = = gNfN
Effective fanout of each stage: f i h g i
Minimum path delay
D g i f i pi NH 1/ N P
Digital
2nd
53
Optimal Number of Stages

For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
D NH
1/ N
Npinv
D
H 1/ N ln H 1/ N H 1/ N pinv 0
N
Substitute best stage effort

Digital
2nd
hH
1 / N
54
Logical Effort
From Sutherland, Sproull

Digital
2nd
55
Example: Optimize Path

1
g=1
f=a
g = 5/3
f = b/a
c
5
g = 5/3
f = c/b
g=1
f = 5/c
Effective fanout, F =
G=
H=
h=
a=
b=
Digital
2nd
56

1
g=1
f=a
g = 5/3
f = b/a
Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59
Digital
2nd
c
5
g = 5/3
f = c/b
g=1
f = 5/c
57

1
g1 = 1
g2 = 5/3
Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g2 = 2.23
c = fb/g3 = 5g4/f = 2.59
Digital
2nd
g3 = 5/3
g4 = 1
58
Example 8-input AND

Digital
2nd
59
Method of Logical Effort

Compute the path effort: F = GBH
Find the best number of stages N ~ log4F
Compute the stage effort f = F1/N

Sketch the path with this number of stages
Work either from either end, find sizes:
Cin = Cout*g/f
Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.

Digital
2nd
60
Summary
Sutherland,
Sproull
Harris

Digital
2nd
61
Ratioed Logic

Digital
2nd
62
Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
F
In1
In2
In3
PDN
VSS
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
PDN
VSS
(a) resistive load
(b) depletion load NMOS
F
In1
In2
In3
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS

Digital
2nd
63
Ratioed Logic
VDD
N transistors + Load
Resistive
Load
VOH = V DD
RL
VOL =
F
In1
In2
In3
RPN + RL
Assymetrical response
PDN
Static power consumption
VSS

Digital
RPN
2nd
tpL= 0.69 RLCL
64
Active Loads
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
PDN
VSS
depletion load NMOS

Digital
2nd
F
In1
In2
In3
PDN
VSS
pseudo-NMOS
65
Pseudo-NMOS
VDD
F
CL
VOH = VDD (similar to complementary CMOS)

V2
k
2
OL
p V
k V
V V
------------- = ----- V
n
DD
Tn OL
DD
Tp
2
2
= V
V 1
OL
DD
T
kp
1 ------ (assuming that V = V
= V
)
T
Tn
Tp
k
n
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Digital
2nd
66
Pseudo-NMOS VTC
3.0
2.5
W/Lp = 4
Vout [V]
2.0
1.5
W/Lp = 2
1.0
0.5
W/Lp = 0.5
W/Lp = 1
W/Lp = 0.25
0.0
0.0
0.5
1.0
1.5
2.0
2.5
Vin [V]
Digital
2nd
67
Improved Loads
VDD
M1
Enable
M2
M1 >> M2
F
A
CL
Adaptive Load
Digital
2nd
68
Improved Loads (2)

VDD
M1
VDD
M2
Out
Out
A
A
B
B
PDN1
PDN2
VSS
VSS
Differential Cascode Voltage Switch Logic (DCVSL)

Digital
2nd
69
DCVSL Example
Out
Out
XOR-NXOR gate
Digital
2nd
70
DCVSL Transient Response
V olta ge [V]
2.5
AB
1.5
0.5
-0.5 0

Digital
2nd
AB
A,B
0.2
A,B
0.4
0.6
Time [ns]
0.8
1.0
71
Pass-Transistor
Logic

Digital
2nd
72
Pass-Transistor Logic
Inputs
B
Switch
Out
Network
Out
B
N transistors
No static consumption

Digital
2nd
73
Example: AND Gate

B
A
B
F = AB
0

Digital
2nd
74
NMOS-Only Logic
3.0
In
VD D
1.5 m/ 0.25 m
0.5 m/0.25 m
Out
0.5 m/0.25 m
Voltage [V]
In
Out
2.0
1.0
0.0
0.5
1.5
Time [ns]

Digital
2nd
75
NMOS-only Switch
C = 2.5V
C = 2.5 V
A = 2.5 V
A = 2.5 V
B
M2
Mn
CL
M1
VB does not pull up to 2.5V, but 2.5V - VTN

Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
Digital
2nd
76
NMOS Only Logic:

Level Restoring Transistor
VDD
Level Restorer
VDD
Mr
B
Mn
M2
X
Out
M1
Advantage: Full Swing

Restorer adds capacitance, takes away pull down current at X
Ratio problem
Digital
2nd
77
Restorer Sizing
Voltage [V]
3.0
2.0
Upper limit on restorer size

Pass-transistor pull-down
can have several transistors
stack
W/Lr =1.75/0.25
W/L r =1.50/0.25
1.0
W/Lr =1.0/0.25
0.0
100

Digital
200
2nd
W/L r =1.25/0.25
300
Time [ps]
400
500
78
Solution 2: Single Transistor Pass Gate with

VT=0
VDD
0V
2.5V
VDD
0V
VDD
Out
2.5V
WATCH OUT FOR LEAKAGE CURRENTS

Digital
2nd
79
Complementary Pass Transistor Logic

A
A
B
B
A
A
B
B
Pass-Transistor
(a)
Inverse
Pass-Transistor
Network
Network
F=AB
F=A+B
F=AB

Digital
F=A+B
AND/NAND
OR/NOR
2nd
F=A
(b)
F=A
EXOR/NEXOR
80
Solution 3: Transmission Gate

C
A
C
A
B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0V

Digital
2nd
81
Resistance of Transmission Gate

30
2. 5 V
Resistance, ohms
Rn
Rp
20
2.5 V
Rn
Vou t
Rp
0V
10
Rn || Rp
0. 0

Digital
1. 0
2nd
Vou t , V
2 .0
82
Pass-Transistor Based Multiplexer

S
VDD
S
VDD
M2
F
S
M1
B
GND
In
1

Digital
2nd
In
2
83
Transmission Gate XOR

B
M2
F
M1
B
M3/M4

Digital
2nd
84
Delay in Transmission Gate Networks

2.5
2.5
V1
In
2.5
Vi
Vi-1
C
2.5
Vn-1
Vi+1
C
Vn
(a)
Req
Req
V1
In
Req
Vi
Vn-1
Vi+1
Req
Vn
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
CC
CC
(c)

Digital
2nd
85
Delay Optimization

Digital
2nd
86
Transmission Gate Full Adder

P
VDD
A
P
B
VDD
Ci
Ci
A
P
Ci
VDD
S Sum Generation
Ci
B
P
A
P
VDD
Co Carry Generation
Ci
Setup
Similar delays for sum and carry

Digital
2nd
87
Dynamic Logic

Digital
2nd
88
Dynamic CMOS
In static circuits at every point in time (except

when switching) the output is connected to
either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage

of signal values on the capacitance of high
impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors

Digital
2nd
89
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
CL
PDN
1
Out
((AB)+C)
A
C
B
Clk
Me
Clk
off
Me on
Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
Digital
2nd
91
Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.
Output can be in the high impedance state

during and after evaluation (PDN off), state is
stored on CL

Digital
2nd
92
Properties of Dynamic Gates
Logic function is implemented by the PDN only

number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect

the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)

reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging C L

Digital
2nd
93
Properties of Dynamic Gates
Overall power dissipation usually higher than static

CMOS
no static current path ever exists between VDD and GND
(including Psc)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals

exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock

Digital
2nd
94
Issues in Dynamic Design 1:

Charge Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Evaluate
VOut
Me
Precharge
Leakage sources
Dominant component is subthreshold current

Digital
2nd
95
Solution to Charge Leakage

Keeper
Clk
Mp
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic

Digital
2nd
96

Charge Sharing
Clk
Mp
Out
CL
B=0
Clk
Charge stored originally on

CL is redistributed (shared)
over CL and CA leading to
reduced robustness
CA
Me
CB

Digital
2nd
97
Charge Sharing Example

Clk
A
Cc=15fF
Ca=15fF
Out
CL=50fF
!B
Cb=15fF
Cd=10fF
Clk

Digital
2nd
98
Charge Sharing
VDD
case 1) if V out < VTn
VDD
Clk
Mp
Mp
Out
Out
CL
=
BB
00
Clk
CL
Ma
Ma
M
Mbb
Mee
M
XX
CC
aa
case 2) if V out > VTn

Ca
--------------------Vout = V DD
Ca + CL
CC
bb

Digital
C V
= C V
t + C V
V
V
L DD
L out
a DD Tn X
or
Ca
V out = Vout t V DD = -------- V DD V Tn V X
CL
2nd
99
Solution to Charge Redistribution

Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)
Digital
2nd
100

Backgate Coupling
Clk
Mp
A=0
Out1 =1
CL1
Out2 =0
CL2
In
B=0
Clk
Me
Dynamic NAND
Digital
2nd
Static NAND
101
Backgate Coupling Effect

3
Voltage
Out1
1
Clk
In
Out2
Time, ns
-1
0

Digital
2nd
102
Issues in Dynamic Design 4: Clock

Feedthrough
Clk
Mp
Out
CL
B
Clk
Me

Digital
2nd
Coupling between Out and

Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.
103
Clock Feedthrough
Clock feedthrough
Clk
2.5
Out
In1
1.5
Voltage
In2
In3
In &
Clk
0.5
In4
Out
Clk
-0.5
0
0.5
Time, ns
Clock feedthrough
Digital
2nd
104
Other Effects
Capacitive
coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)

Digital
2nd
105
Cascading Dynamic Gates

V
Clk
Mp
Clk
Mp
Out1
Me
Out2
In
In
Clk
Clk
Clk
Me
Out1
VTn
V
Out2
t
Only 0 1 transitions allowed at inputs!

Digital
2nd
106
Domino Logic
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me

Digital
2nd
Out1
Clk
00
01
In4
In5
Clk
Mp Mkp
Out2
PDN
Me
107
Why Domino?
Clk
Ini
Inj
Clk
Ini
Inj
PDN
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Like falling dominos!

Digital
2nd
108
Properties of Domino Logic

Only non-inverting logic can be implemented
Very high speed
static inverter can be skewed, only L-H transition

Input capacitance reduced smaller logical effort

Digital
2nd
109
Designing with Domino Logic

VDD
VDD
VDD
Clk
Mp
Clk
Out1
Mp
Mr
Out2
In1
In2
PDN
PDN
In4
In3
Can be eliminated!
Clk
Me
Clk
Me
Inputs = 0
during precharge
Digital
2nd
110
Footless Domino
VDD
Clk
VDD
Mp
Clk
Clk
Out2
In1
1
Mp
Out1
1
In2
VDD
Mp
Outn
1
0
In3
Inn
The first gate in the chain needs a foot switch

Precharge is rippling short-circuit current
A solution is to delay the clock for each stage
Digital
2nd
111
Differential (Dual Rail) Domino

off
Mp Mkp
Clk
Out = AB
on
Mkp
Clk
Mp
!A
Out = AB
!B
B
Clk
Me
Solves the problem of non-inverting logic

Digital
2nd
112
np-CMOS
Mp
Clk
In1
In2
In3
11
10
PDN
Clk
Me
Out1
Clk
Me
In4
In5
PUN
00
01
Clk
Mp
Out2
(to PDN)
Only 0 1 transitions allowed at inputs of PDN

Only 1 0 transitions allowed at inputs of PUN
Digital
2nd
113
NORA Logic
Mp
Clk
In1
In2
In3
11
10
Out1
PDN
Clk
Clk
Me
In4
In5
PUN
00
01
Clk
Me
to other
PDNs
Mp
Out2
(to PDN)
to other
PUNs
WARNING: Very sensitive to noise!

Digital
2nd
114

Digital Integrated Circuits

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Digital Integrated

Combinational vs. Sequential Logic

Static CMOS Circuit

EE141 Integrated Circuits

Static Complementary CMOS

PUN and PDN are dual logic networks

EE141 Integrated Circuits

Transistors can be thought as a switch controlled by its gate signal

NMOS Transistors pass a strong 0 but a weak 1

PMOS Transistors pass a strong 1 but a weak 0

EE141 Integrated Circuits

Complementary CMOS Logic Style

EE141 Integrated Circuits

Example Gate: NAND

EE141 Integrated Circuits

Example Gate: NOR

EE141 Integrated Circuits

Complex CMOS Gate

EE141 Integrated Circuits

Constructing a Complex Gate

(b) Deriving the pull-up network

(c) complete gate

EE141 Integrated Circuits

General purpose logic

For regular, structured designs (arithmetic)

Standard Cell Layout Methodology

EE141 Integrated Circuits

Standard Cell Layout Methodology

EE141 Integrated Circuits

Cell height 12 metal tracks

EE141 Integrated Circuits

EE141 Integrated Circuits

2-input NAND gate

EE141 Integrated Circuits

EE141 Integrated Circuits

EE141 Integrated Circuits

EE141 Integrated Circuits

Consistent Euler Path

EE141 Integrated Circuits

OAI22 Logic Graph

EE141 Integrated Circuits

(a) Logic graphs for (ab+cd)

(b) Euler Paths {a b c d}

(c) stick diagram for ordering {a b c d}

EE141 Integrated Circuits

Two fingers (folded)

Less diffusion capacitance

EE141 Integrated Circuits

Properties of Complementary CMOS Gates

EE141 Integrated Circuits

EE141 Integrated Circuits

Switch Delay Model

Input Pattern Effects on Delay

both inputs go low

delay is 0.69 Rp/2 CL

one input goes low

High to low transition

EE141 Integrated Circuits

Delay Dependence on Input Patterns

EE141 Integrated Circuits

Transistor Sizing a Complex

EE141 Integrated Circuits

EE141 Integrated Circuits