Single Cycle Control

Recap:The MIPS Instruction Formats

All MIPS instructions are 32 bits long. The three instruction

31
26
21
16
11
6
0
formats:
R-type
I-type
J-type

op
6 bits
31
26

rs
5 bits
21

rt
5 bits
16

op
6 bits
31
26
op

rs
5 bits

rt
5 bits

6 bits

rd
5 bits

shamt
5 bits

funct
6 bits

immediate
16 bits

target address
26 bits

The different fields are:

op: operation of the instruction

rs, rt, rd: the source and destination registers specifier
shamt: shift amount
funct: selects the variant of the operation in the op field
address / immediate: address offset or immediate value
target address: target address of the jump instruction

Recap: The MIPS Subset

31

ADD and subtract

add rd, rs, rt
sub rd, rs, rt

OR Imm:

26
op
6 bits

31

rs
5 bits

26
op
6 bits

ori rt, rs, imm16

21

16
rt
5 bits

21
rs
5 bits

11
rd
5 bits

6
shamt
5 bits

16
rt
5 bits

0
funct
6 bits

0
immediate
16 bits

LOAD and STORE

lw rt, rs, imm16
sw rt, rs, imm16

BRANCH:
beq rs, rt, imm16

JUMP:
j target

31

26
op
6 bits

0
target address
26 bits

Recap: A Single Cycle Datapath

We have everything except control signals (underline)

Well see how to generate the control signals

Instruction<31:0>

RegWr 5

Rs Rt
5
5
busA

32

ExtOp

Data In32

ALUSrc

Rd

Clk

Imm16
MemtoReg

MemWr

WrEn Adr
Data
Memory

32

Mux

16

Extender

imm16

Rs

32

Mux

32
Clk

Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

Zero

ALU

busW

Rt

ALUct
r

<0:15>

1 Mux 0

<11:15>

RegDst

Rt

<16:20>

Rd

Instruction
Fetch Unit

Jump
Clk

<21:25>

Branch

The Big Picture: Where are We Now?

Processor
Input

Control

Datapath

Memory
Output

RTL: The ADD Instruction

31

26
op
6 bits

add

21
rs

16
rt

5 bits

5 bits

11
rd
5 bits

shamt

funct

5 bits

6 bits

rd, rs, rt

mem[PC]

Fetch the instruction from memory

R[rd] <- R[rs] + R[rt]

PC <- PC + 4

The actual operation

Calculate the next instructions address

Instruction Fetch Unit at the Beginning of

Add / Subtract

Fetch the instruction from Instruction memory: Instruction

<- mem[PC]
This is the same for all instructions
30
30

PC<31:28>

Mux

imm16
16
Instruction<15:0>

SignExt

Clk

30

Adder

Adder

PC

30

30

00

Mux

Target 4
Instruction<25:0>
26

Addr<31:2>
Addr<1:0>
Instruction
Memory
32

Jump = previous
Instruction<31:0>

30

30
Branch = previous
Zero = previous

The Single Cycle Datapath during Add

and 31Subtract
26
21
16
11
6
0
op

rs

rt

rd

shamt

R[rd] <- R[rs] + / - R[rt]

Instruction<31:0>

ExtOp = x

32

Imm16

32

Data In32

ALUSrc = 0

Rd

Clk

WrEn Adr
Data
Memory

32

Mux

16

Extender

imm16

Rs

MemtoReg = 0
Zero MemWr = 0

Mux

32
Clk

ALU

busW

busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

Rt

<0:15>

RegWr = 1 5

ALUctr = Add
or Subtract

Rs Rt
5
5

<11:15>

1 Mux 0

<16:20>

RegDst = 1

Rt

Instruction
Fetch Unit

Jump = 0
Clk

<21:25>

Branch = 0
Rd

funct

Instruction Fetch Unit at the End of

Add/Subtract

PC <- PC + 4
This is the same for all instructions except: Branch and Jump
30
30

PC<31:28>

Mux

imm16
16
Instruction<15:0>

SignExt

Clk

30

Adder

Adder

PC

30

30

00

Mux

Target 4
Instruction<25:0>
26

Jump = 0

30

30
Branch = 0 Zero = x

Addr<31:2>
Addr<1:0>
Instruction
Memory
32

Instruction<31:0>

What about OR Immediately??

Control signals for Load, Store, Branch & Jump

The Single Cycle Datapath during Load

31

26
op

21
rs

16

rt

immediate

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Instruction<31:0>

32

Imm16
MemtoReg = 1
Zero MemWr = 0
0

32

Data In32

ALUSrc = 1

Rd

Clk

Mux

ExtOp = 1

Rs

<0:15>

16

Extender

imm16

Rt

ALU

busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

ALUct
r=
Add

Mux

32
Clk

Rs Rt
5
5

<11:15>

1 Mux 0

RegWr = 1 5
busW

Rt

<16:20>

RegDst = 0

Rd

Instruction
Fetch Unit

Jump = 0
Clk

<21:25>

Branch = 0

WrEn Adr
Data
Memory

32

The Single Cycle Datapath during Store

31

26
op

21

16

rs

rt

immediate

Imm16

MemtoReg = x
Zero MemWr = 1
0

32

Data In 32

32
ALUSrc = 1

Rd

Clk

WrEn Adr
Data
Memory

32

Mux

ExtOp = 1

Rs

<0:15>

16

Extender

imm16

Rt

ALU

busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

ALUct
r=
Add

Mux

32
Clk

Rs Rt
5
5

<11:15>

1 Mux 0

RegWr = 0 5
busW

Rt

<16:20>

RegDst = x

Rd

Instruction
Fetch Unit

Jump = 0
Clk

<21:25>

Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Instruction<31:0>
Branch = 0

The Single Cycle Datapath during Branch

31

26
op

21
rs

16

rt

immediate

32

Imm16
MemtoReg = x
Zero MemWr = 0
0

32

Data In32

ALUSrc = 0

Rd

Clk

WrEn Adr
Data
Memory

32

Mux

ExtOp = x

Rs

<0:15>

16

Extender

imm16

ALU

busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

Rt

Mux

32
Clk

ALUctr =
Subtract

Rs Rt
5
5

<11:15>

1 Mux 0

RegWr = 0
busW

Rt

<16:20>

RegDst = x

Rd

Instruction
Fetch Unit

Jump = 0
Clk

<21:25>

if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

Instruction<31:0>
Branch = 1

Instruction Fetch Unit at the End of Branch

31

26
op

21

16

rs

rt

immediate

if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC +

4
30
30

PC<31:28>

30

Mux

imm16
16
Instruction<15:0>

SignExt

Clk

30

Adder

Adder

PC

30

30

00

Mux

Target 4
Instruction<25:0>
26

Addr<31:2>
Addr<1:0>
Instruction
Memory

Jump = 0

32

Instruction<31:0>

30
Assume Zero = 1 to see
the interesting case.

Branch = 1 Zero = 1

The Single Cycle Datapath during Jump

31

26

op

target address

Imm16

Data In32

ALUSrc = x

32

Clk

WrEn Adr
Data
Memory

32

Mux

ExtOp = x

32

Rd

<0:15>

16

Extender

imm16

ALU

busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
1

Rs

MemtoReg = x
Zero MemWr = 0

Mux

32
Clk

Rt

ALUctr = x

Rs Rt
5
5

<11:15>

1 Mux 0

RegWr = 0 5
busW

Rt

<16:20>

RegDst = x

Rd

Instruction
Fetch Unit

Jump = 1
Clk

<21:25>

Nothing to do! Make sure control signals are set correctly!

Instruction<31:0>
Branch = 0

Instruction Fetch Unit at the End of Jump

31

26

op

target address

PC <- PC<31:29> concat target<25:0> concat 00

30
30

PC<31:28>

Mux

imm16
16
Instruction<15:0>

SignExt

Clk

30

Adder

Adder

PC

30

30

00

Mux

Target 4
Instruction<25:0>
26

Jump = 1

30

30
Branch = 0 Zero = x

Addr<31:2>
Addr<1:0>
Instruction
Memory
32

Instruction<31:0>

A Summary of the Control Signals

See
Appendix A

func 10 000010 0010

Dont Care

op 00 000000 000000 110110 001110 101100 010000 0010

add
sub
ori
lw
sw
beq jump
1
1
0
0
x
x
x

RegDst

ALUSrc
MemtoReg
RegWrite

0
0
1

0
0
1

1
0
1

1
1
1

1
x
0

0
x
0

x
x
0

MemWrite
Branch
Jump

0
0
0

0
0
0

0
0
0

0
0
0

1
0
0

0
1
0

0
0
1

ExtOp
ALUctr<2:0>
31

x
x
0
Add Subtract Or

26

21

1
Add

16

R-type

op

rs

rt

I-type

op

rs

rt

J-type

op

1
x
x
Add Subtract xxx

11
rd

6
shamt

immediate
target address

0
funct

add, sub
ori, lw, sw, beq
jump

Building a local controller: ALU Control

The Concept of Local Decoding

op
RegDst

00 0000
R-type
1

00 110110 001110 101100 010000 0010

ori
lw
sw
beq jump
0
0
x
x
x

ALUSrc
MemtoReg
RegWrite

0
0
1

1
0
1

1
1
1

1
x
0

0
x
0

x
x
0

MemWrite
Branch
Jump

0
0
0

0
0
0

0
0
0

1
0
0

0
1
0

0
0
1

x
R-type

0
Or

1
Add

ExtOp
ALUop<N:0>

func
op
6

Main
Control

ALU
Control
(Local)

ALUctr
3

ALU

6
ALUop
N

1
x
x
Add Subtract xxx

The Encoding of ALUop

op
6

Main
Control

func
6
ALUop

ALU
ALUctr
Control
3
(Local)

In this exercise, ALUop has to be 2 bits wide to

represent:
(1) R-type instructions
I-type instructions that require the ALU to perform:
(2) Or, (3) Add, and (4) Subtract

To implement the full MIPS ISA, ALUop has to be 3

bits to represent:
(1) R-type instructions
I-type instructions that require the ALU to perform:
(2) Or, (3) Add,R-type
(4) Subtract,
andi)
ori and
lw(5) And
sw (Example:
beq jump
ALUop (Symbolic)
ALUop<2:0>

R-type
1 00

Or
0 10

Add
0 00

Add Subtract xxx

0 00
0 01 xxx

The Decoding of the func Field

op
6

func
6
ALUop
N

Main
Control

ALU
ALUctr
Control
3
(Local)

R-type

ori

lw

sw

ALUop (Symbolic)
ALUop<2:0>

R-type
1 00

Or
0 10

Add
0 00

Add Subtract xxx

0 00
0 01 xxx

31

21

R-type

26
op

rs

funct<5:0>Instruction Operation

10 0101
10 1010

add
subtract
and
or
set-on-less-than

rt

11
rd

jump

6
shamt

0
funct

ALUct ALUctr<2:0> ALU Operation

r
000
Add
001
Subtract

ALU

10 0000
10 0010
10 0100

16

beq

010
110
111

And
Or
Set-on-less-than

The Truth Table for ALUctr

R-type
ALUop
(Symbolic) R-type
ALUop<2:0> 1 00

ori
Or
0 10

lw
Add
0 00

funct<3:0> Instruction Op.

0000
add
sw
beq
Add Subtract
0 00
0 01

0010
0100
0101

subtract
and
or

1010

set-on-less-than

ALUop
func
ALU
ALUctr
bit<2>bit<1>bit<0> bit<3>bit<2>bit<1>bit<0> Operation bit<2>bit<1>bit<0>
0
0
0

0
x
1

0
1
x

x
x
x

x
x
x

x
x
x

x
x
x

Add
Subtract
Or

0
1
0

1
1
0

0
0
1

1
1
1

x
x
x

x
x
x

0
0
0

0
0
1

0
1
0

0
0
0

Add
Subtract
And

0
1
0

1
1
0

0
0
0

1
1

x
x

x
x

0
1

1
0

0
1

1
0

Or
Set on <

0
1

0
1

1
1

The Logic Equation for ALUctr<2>

ALUop
func
bit<2>bit<1>bit<0> bit<3>bit<2>bit<1>bit<0> ALUctr<2>
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

This makes func<3> a dont care

ALUctr<2> = !ALUop<2> & ALUop<0> +
ALUop<2> & !func<2> & func<1> & !func<0>

ALUop
func
bit<2>
bit<1>
bit<0> bit<3>
bit<2>
bit<1>
bit<0>ALUctr<1>
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
ALUctr<1> = !ALUop<2> & !ALUop<0> +
ALUop<2> & !func<2> & !func<0>

The Logic Equation for ALUctr<0>

ALUop
func
bit<2>
bit<1>
bit<0> bit<3>
bit<2>
bit<1>
bit<0>ALUctr<0>
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1

ALUctr<0> = !ALUop<2> & ALUop<0>

+ ALUop<2> & !func<3> & func<2> & !func<1> & func<0>
+ ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

The ALU Control Block

func
6
ALUop
3

ALU
ALUctr
Control
3
(Local)

ALUctr<2> = !ALUop<2> & ALUop<0> +

ALUop<2> & !func<2> & func<1> & !func<0>

ALUctr<1> = !ALUop<2> & !ALUop<0> +

ALUop<2> & !func<2> & !func<0>

ALUctr<0> = !ALUop<2> & ALUop<0>

+ ALUop<2> & !func<3> & func<2> & !func<1> &
func<0>
+ ALUop<2> & func<3> & !func<2> & func<1> & !
func<0>

The main controller

The Truth Table for the Main Control

op
6

Main
Control

op
RegDst

RegDst
ALUSrc

func
6

ALUctr
ALU
3
Control
(Local)

ALUop
3
00 0000
R-type
1

00 110110 001110 101100 010000 0010

ori
lw
sw
beq jump
0
0
x
x
x

ALUSrc
MemtoReg
RegWrite

0
0
1

1
0
1

1
1
1

1
x
0

0
x
0

x
x
0

MemWrite
Branch
Jump

0
0
0

0
0
0

0
0
0

1
0
0

0
1
0

0
0
1

x
R-type
1

0
Or
0

1
Add
0

0
0

1
0

0
0

ExtOp
ALUop (Symbolic)
ALUop <2>
ALUop <1>
ALUop <0>

1
x
x
Add Subtract xxx
0
x
0
0
x
0
0
x
1

Example: The Truth Table for RegWrite

op

00 0000
R-type

RegWrite

00 110110 001110 101100 010000 0010

ori
lw
sw
beq jump

RegWrite = R-type + ori + lw

= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0>
+ !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0>
+ op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0>
op<5>
.

op<5>
.

<0>

R-type

op<5>
.

<0>

ori

op<5>
.

<0>

lw

op<5>
.

<0>

sw

op<5>
.

<0>

beq

(R-type)
(ori)
(lw)

.
op<0>

jump
RegWrite

Putting it All Together: A Single Cycle

Processor
ALUop
RegDst

op
Main
Control
6
Instr<31:26>

Rt
Rs Rt
5
5

busA

32

ExtOp

Data In32

ALUSrc

Rd

Clk

Imm16
MemtoReg

MemWr

WrEn Adr
Data
Memory

32

Mux

Extender

imm16
Instr<15:0> 16

Rs

32

Mux

32
Clk

Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

Zero

ALU

busW

Rt

ALUct
r

<0:15>

Instruction
Fetch Unit

Jump
Clk

<11:15>

Instruction<31:0>

Branch

1 Mux 0
RegWr 5

func
Instr<5:0>6

<16:20>

RegDst

ALUSrc

ALU
ALUctr
Control
3

<21:25>

Rd

Drawback of this Single Cycle

Processor
Long cycle time:
Cycle time must be long enough for the load instruction:
PCs Clock -to-Q +
Instruction Memory Access Time +
Register File Access Time +
ALU Delay (address calculation) +
Data Memory Access Time +
Register File Setup Time +
Clock Skew

Cycle time is much longer than needed for all other

instructions