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op
6 bits
31
26
rs
5 bits
21
rt
5 bits
16
op
6 bits
31
26
op
rs
5 bits
rt
5 bits
6 bits
rd
5 bits
shamt
5 bits
funct
6 bits
immediate
16 bits
target address
26 bits
31
OR Imm:
26
op
6 bits
31
rs
5 bits
26
op
6 bits
21
16
rt
5 bits
21
rs
5 bits
11
rd
5 bits
6
shamt
5 bits
16
rt
5 bits
0
funct
6 bits
0
immediate
16 bits
BRANCH:
beq rs, rt, imm16
JUMP:
j target
31
26
op
6 bits
0
target address
26 bits
Instruction<31:0>
RegWr 5
Rs Rt
5
5
busA
32
ExtOp
Data In32
ALUSrc
Rd
Clk
Imm16
MemtoReg
MemWr
WrEn Adr
Data
Memory
32
Mux
16
Extender
imm16
Rs
32
Mux
32
Clk
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
Zero
ALU
busW
Rt
ALUct
r
<0:15>
1 Mux 0
<11:15>
RegDst
Rt
<16:20>
Rd
Instruction
Fetch Unit
Jump
Clk
<21:25>
Branch
Processor
Input
Control
Datapath
Memory
Output
26
op
6 bits
add
21
rs
16
rt
5 bits
5 bits
11
rd
5 bits
shamt
funct
5 bits
6 bits
rd, rs, rt
mem[PC]
PC<31:28>
Mux
imm16
16
Instruction<15:0>
SignExt
Clk
30
Adder
Adder
PC
30
30
00
Mux
Target 4
Instruction<25:0>
26
Addr<31:2>
Addr<1:0>
Instruction
Memory
32
Jump = previous
Instruction<31:0>
30
30
Branch = previous
Zero = previous
rs
rt
rd
shamt
Instruction<31:0>
ExtOp = x
32
Imm16
32
Data In32
ALUSrc = 0
Rd
Clk
WrEn Adr
Data
Memory
32
Mux
16
Extender
imm16
Rs
MemtoReg = 0
Zero MemWr = 0
Mux
32
Clk
ALU
busW
busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
Rt
<0:15>
RegWr = 1 5
ALUctr = Add
or Subtract
Rs Rt
5
5
<11:15>
1 Mux 0
<16:20>
RegDst = 1
Rt
Instruction
Fetch Unit
Jump = 0
Clk
<21:25>
Branch = 0
Rd
funct
PC <- PC + 4
This is the same for all instructions except: Branch and Jump
30
30
PC<31:28>
Mux
imm16
16
Instruction<15:0>
SignExt
Clk
30
Adder
Adder
PC
30
30
00
Mux
Target 4
Instruction<25:0>
26
Jump = 0
30
30
Branch = 0 Zero = x
Addr<31:2>
Addr<1:0>
Instruction
Memory
32
Instruction<31:0>
26
op
21
rs
16
rt
immediate
32
Imm16
MemtoReg = 1
Zero MemWr = 0
0
32
Data In32
ALUSrc = 1
Rd
Clk
Mux
ExtOp = 1
Rs
<0:15>
16
Extender
imm16
Rt
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
ALUct
r=
Add
Mux
32
Clk
Rs Rt
5
5
<11:15>
1 Mux 0
RegWr = 1 5
busW
Rt
<16:20>
RegDst = 0
Rd
Instruction
Fetch Unit
Jump = 0
Clk
<21:25>
Branch = 0
WrEn Adr
Data
Memory
32
26
op
21
16
rs
rt
immediate
Imm16
MemtoReg = x
Zero MemWr = 1
0
32
Data In 32
32
ALUSrc = 1
Rd
Clk
WrEn Adr
Data
Memory
32
Mux
ExtOp = 1
Rs
<0:15>
16
Extender
imm16
Rt
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
ALUct
r=
Add
Mux
32
Clk
Rs Rt
5
5
<11:15>
1 Mux 0
RegWr = 0 5
busW
Rt
<16:20>
RegDst = x
Rd
Instruction
Fetch Unit
Jump = 0
Clk
<21:25>
26
op
21
rs
16
rt
immediate
32
Imm16
MemtoReg = x
Zero MemWr = 0
0
32
Data In32
ALUSrc = 0
Rd
Clk
WrEn Adr
Data
Memory
32
Mux
ExtOp = x
Rs
<0:15>
16
Extender
imm16
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
Rt
Mux
32
Clk
ALUctr =
Subtract
Rs Rt
5
5
<11:15>
1 Mux 0
RegWr = 0
busW
Rt
<16:20>
RegDst = x
Rd
Instruction
Fetch Unit
Jump = 0
Clk
<21:25>
26
op
21
16
rs
rt
immediate
PC<31:28>
30
Mux
imm16
16
Instruction<15:0>
SignExt
Clk
30
Adder
Adder
PC
30
30
00
Mux
Target 4
Instruction<25:0>
26
Addr<31:2>
Addr<1:0>
Instruction
Memory
Jump = 0
32
Instruction<31:0>
30
Assume Zero = 1 to see
the interesting case.
Branch = 1 Zero = 1
26
op
target address
Imm16
Data In32
ALUSrc = x
32
Clk
WrEn Adr
Data
Memory
32
Mux
ExtOp = x
32
Rd
<0:15>
16
Extender
imm16
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
1
Rs
MemtoReg = x
Zero MemWr = 0
Mux
32
Clk
Rt
ALUctr = x
Rs Rt
5
5
<11:15>
1 Mux 0
RegWr = 0 5
busW
Rt
<16:20>
RegDst = x
Rd
Instruction
Fetch Unit
Jump = 1
Clk
<21:25>
26
op
target address
PC<31:28>
Mux
imm16
16
Instruction<15:0>
SignExt
Clk
30
Adder
Adder
PC
30
30
00
Mux
Target 4
Instruction<25:0>
26
Jump = 1
30
30
Branch = 0 Zero = x
Addr<31:2>
Addr<1:0>
Instruction
Memory
32
Instruction<31:0>
Dont Care
RegDst
ALUSrc
MemtoReg
RegWrite
0
0
1
0
0
1
1
0
1
1
1
1
1
x
0
0
x
0
x
x
0
MemWrite
Branch
Jump
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
ExtOp
ALUctr<2:0>
31
x
x
0
Add Subtract Or
26
21
1
Add
16
R-type
op
rs
rt
I-type
op
rs
rt
J-type
op
1
x
x
Add Subtract xxx
11
rd
6
shamt
immediate
target address
0
funct
add, sub
ori, lw, sw, beq
jump
00 0000
R-type
1
ALUSrc
MemtoReg
RegWrite
0
0
1
1
0
1
1
1
1
1
x
0
0
x
0
x
x
0
MemWrite
Branch
Jump
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
x
R-type
0
Or
1
Add
ExtOp
ALUop<N:0>
func
op
6
Main
Control
ALU
Control
(Local)
ALUctr
3
ALU
6
ALUop
N
1
x
x
Add Subtract xxx
Main
Control
func
6
ALUop
ALU
ALUctr
Control
3
(Local)
R-type
1 00
Or
0 10
Add
0 00
func
6
ALUop
N
Main
Control
ALU
ALUctr
Control
3
(Local)
R-type
ori
lw
sw
ALUop (Symbolic)
ALUop<2:0>
R-type
1 00
Or
0 10
Add
0 00
31
21
R-type
26
op
rs
funct<5:0>Instruction Operation
10 0101
10 1010
add
subtract
and
or
set-on-less-than
rt
11
rd
jump
6
shamt
0
funct
ALU
10 0000
10 0010
10 0100
16
beq
010
110
111
And
Or
Set-on-less-than
R-type
ALUop
(Symbolic) R-type
ALUop<2:0> 1 00
ori
Or
0 10
lw
Add
0 00
0010
0100
0101
subtract
and
or
1010
set-on-less-than
ALUop
func
ALU
ALUctr
bit<2>bit<1>bit<0> bit<3>bit<2>bit<1>bit<0> Operation bit<2>bit<1>bit<0>
0
0
0
0
x
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
Add
Subtract
Or
0
1
0
1
1
0
0
0
1
1
1
1
x
x
x
x
x
x
0
0
0
0
0
1
0
1
0
0
0
0
Add
Subtract
And
0
1
0
1
1
0
0
0
0
1
1
x
x
x
x
0
1
1
0
0
1
1
0
Or
Set on <
0
1
0
1
1
1
ALUop
func
bit<2>bit<1>bit<0> bit<3>bit<2>bit<1>bit<0> ALUctr<2>
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
ALUop
func
bit<2>
bit<1>
bit<0> bit<3>
bit<2>
bit<1>
bit<0>ALUctr<1>
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
ALUctr<1> = !ALUop<2> & !ALUop<0> +
ALUop<2> & !func<2> & !func<0>
ALUop
func
bit<2>
bit<1>
bit<0> bit<3>
bit<2>
bit<1>
bit<0>ALUctr<0>
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1
ALU
ALUctr
Control
3
(Local)
Main
Control
op
RegDst
RegDst
ALUSrc
func
6
ALUctr
ALU
3
Control
(Local)
ALUop
3
00 0000
R-type
1
ALUSrc
MemtoReg
RegWrite
0
0
1
1
0
1
1
1
1
1
x
0
0
x
0
x
x
0
MemWrite
Branch
Jump
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
x
R-type
1
0
Or
0
1
Add
0
0
0
1
0
0
0
ExtOp
ALUop (Symbolic)
ALUop <2>
ALUop <1>
ALUop <0>
1
x
x
Add Subtract xxx
0
x
0
0
x
0
0
x
1
op
00 0000
R-type
RegWrite
op<5>
.
<0>
R-type
op<5>
.
<0>
ori
op<5>
.
<0>
lw
op<5>
.
<0>
sw
op<5>
.
<0>
beq
(R-type)
(ori)
(lw)
.
op<0>
jump
RegWrite
op
Main
Control
6
Instr<31:26>
Rt
Rs Rt
5
5
busA
32
ExtOp
Data In32
ALUSrc
Rd
Clk
Imm16
MemtoReg
MemWr
WrEn Adr
Data
Memory
32
Mux
Extender
imm16
Instr<15:0> 16
Rs
32
Mux
32
Clk
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32
Zero
ALU
busW
Rt
ALUct
r
<0:15>
Instruction
Fetch Unit
Jump
Clk
<11:15>
Instruction<31:0>
Branch
1 Mux 0
RegWr 5
func
Instr<5:0>6
<16:20>
RegDst
ALUSrc
ALU
ALUctr
Control
3
<21:25>
Rd