Multicycle Datapath

Recap: A Single Cycle Processor

ALUop
RegDst

op
Main
Control
6
Instr<31:26>

Rt

ALUctr
busA

1
32

ExtOp

Clk

Imm16
MemtoReg

MemWr

32

Data In32

ALUSrc

Rd

WrEn Adr

32

Mux

Extender

imm16
Instr<15:0> 16

32

Mux

32
Clk

Rw Ra Rb
32 32-bit
Registers
busB
32

ALU

busW

Zero

Rs

<0:15>

Rt

<11:15>

Clk

1 Mux 0
RegWr 5

Instruction
Fetch Unit

Jump

Rt
Rs

Instruction<31:0>

Branch

<16:20>

RegDst

func
Instr<5:0>6

ALUSrc

ALU
ALUctr
Control
3

<21:25>

Rd

Data
Memory

The Main Control

op<5>
.

op<5>
.

<0>

R-type

op<5>
.

<0>

ori

op<5>
.

<0>

lw

op<5>
.

<0>

sw

op<5>
.

<0>

beq

jump

.
op<0>

RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUop<2>
ALUop<1>
ALUop<0> 3

Recap: Drawbacks of this Single Cycle

Processor
Long cycle time:
Cycle time must be long enough for the load
instruction:
PCs Clock -to-Q +
Instruction Memory Access Time +
Register File Access Time +
ALU Delay (address calculation) +
Data Memory Access Time +
Register File Setup Time +
Clock Skew
Cycle time is much longer than needed for all other
instructions. Examples:
R-type instructions do not require data memory
access
Jump does not require ALU operation nor data

Introduction to the Concept of Multiple

Cycle Processor

Overview of a
Implementation

Multiple

Cycle

The root of the single cycle processors problems:

The cycle time has to be long enough for the
slowest instruction
Solution:
Break the instruction into smaller steps
Execute each step (instead of the entire
instruction) in one cycle
Cycle time: time it takes to execute the
longest step
Keep all the steps to have similar length
This is the essence of the multiple cycle processor
6

Overview
of
Implementation

Multiple

Cycle

The advantages of the multiple cycle

processor:
Cycle time is much shorter
Different instructions take different
number of cycles to complete
E.g.
Load takes five cycles
Jump only takes three cycles
Allows a functional unit to be used more
than once per instruction
7

The Five Steps of a Load

Instruction
Instruction Fetch
Instr Decode / Address Data MemoryReg Wr
Reg. Fetch

Clk
Old
Value
Rs, Rt, Rd,
Op, Func

PC

ALUctr
ExtOp

RegWr
busA
busB

Old
DelayValue
through Extender & Mux
Old
Value

Addre
ss

Old
Value

busW

Old

New
Value
New
Value
ALU
Delay

Data Memory Access Time

New
Value
New

Register File Write Time

ALUSrc

Clk-to-Q
New
Value
Instruction Memory Access Time
Old
New
Value
Value Delay through Control Logic
Old
New
Value
Value
Old
New
Value
Value
Old
New
Value
Value
Old
New
Value
Value File Access Time
Register

Register File & Memory Write Timing: Ideal

vs. Reality
In previous lectures, register file and memory are simplified:
Write happens at the clock tick
WrEn
Address, data, and write enable must be
Adr
stable one set-up time before the clock tick 32 Ideal
Memory
32

Din Dout

32

In real life:
Neither register file nor ideal memory has the clockClk
input
The write path is a combinational logic delay path:
Write enable goes to 1 and Din settles down
Memory write access delay
WrEn
Din is written into Mem[address]
Adr
32
Ideal
Important: Address and Data must be
Memory
stable BEFORE Write Enable goes to 1
32

Din Dout

32

Race Condition Between Address and Write Enable

This real (no clock input) register file may notRaRegWr
5
work reliably in the single cycle processor because
Rb :busA
We cannot guarantee Rw will
be stable BEFORE RegWr = 1
There is a race between Rw (address)
and RegWr (write enable)

Reg File

32

Rw busB
32
busW

5
32

The real (no clock input) memory may not workWrEn

Adr
reliably in the single cycle processor because:32 Ideal
We cannot guarantee Address will
be stable BEFORE WrEn = 1
There is a race between Adr and WrEn

Memory
32

Din Dout

32

10

How
to
Condition?

Avoid

this

Race

Solution for the multiple cycle implementation:

Make sure Address is stable by the end of
Cycle N
Assert Write Enable signal ONE cycle later at
Cycle (N + 1)
Address cannot change until Write Enable is
disasserted

11

Dual-Port Ideal Memory: IM + DM

Dual Port Ideal Memory

Independent Read (RAdr, Dout) and Write
(WAdr, Din) ports
Read and write (to different location) can occur
at the same cycle
Read Port is a combinational path:
Read Address Valid -->
MemWr
Memory Read Access Delay -->
00
Data Out Valid
RAdr<1:0>
Write Port is also a combinational path:30 <31:2>
Ideal
MemWrite = 1 -->
32 Memory
WrAdr
Memory Write Access Delay -->
DataIn is written into location[WrAdr]32 Din Dout 32

12

Instruction Fetch Cycle: In

Beginning
Every cycle begins right AFTER the clock tick:
mem[PC]

the

PC<31:0> + 4

Clk
One Logic Clock Cycle

we are here!
PCWr=?

PC

MemWr=?

32

IRWr=?

RAdr

Ideal
Memory
32
32

WrAdr
Din

Dout
32

Instruction Reg

Clk

32

ALU

32

32

4
32

32

ALU
Control
ALUop=?

Clk

13

Instruction Fetch Cycle: The End

Every cycle ends at the next clock tick (storage
element updates):
IR <-- mem[PC] ; PC<31:0> <-- PC<31:0> + 4
Clk
One Logic Clock Cycle
We are here!

PCWr=1

PC

MemWr=0 IRWr=1
32

32

32

Instruction Reg

Clk

32

RAdr

Ideal
Memory
WrAdr
Din Dout

ALU

32

0
0

32

32

32

ALU
Control

ALUOp = Add

32

Clk

14

Instruction Fetch Cycle: Overall Picture

Cycle 1
Ifetch

PCWr=1

ALUOp=Add
1: PCWr, IRWr
x: PCWrCond
RegDst, Mem2R
Others: 0s

PCWrCond=x

32

PC

WrAdr
32
Din Dout

32
32

busA
32
busB 32

32

32

0
1
2
3

ALUSelB=00

Target
Zero

ALU

Ideal
Memory

Mux

RAdr

Instruction Reg

Mux

32

1
0

32
32

ALUSelA=0

BrWr=0

Mux

Zero
IorD=0 MemWr=0
IRWr=1

PCSrc=0

32
32

ALU
Control
15
ALUOp=Add

Register Fetch/Instruction Decode: Cycle 2

busA <- RegFile[rs] ; busB <- RegFile[rt] ;
ALU is not being used: ALUctr = xx
PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

Go to theOp
ControlFunc

32

Rt
Rt

Mux

Ideal
Memory

Rd

Imm

16

Ra
Rb busA

Reg File

32

Rw
busWbusB 32

32

0
1
2
3

Zero

ALU

RAdr

Rs

32

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x
Zero
IorD=x MemWr=0
IRWr=0RegDst=xRegWr=0ALUSelA=x 1

32
32

ALU
Control

ALUSelB=xx
16
ALUOp=xx

Register Fetch / Instruction Decode: Cycle 2

(Continue)
Rfetch/Decode

busA <- Reg[rs] ; busB <- Reg[rt] ALUOp=Add

;
1: BrWr, ExtOp
Target <- PC + SignExt(Imm16)*4
ALUSelB=10
PCWr=0

x: RegDst, PCSrc
IorD, MemtoReg
Others: 0s

PCWrCond=0
Zero

PCSrc=x

32

PC

WrAdr
32
Din Dout

32
32

Rt 0

Rd

Ra
Rb

busA

Reg File

32

Rw
busWbusB 32

<< 2

Beq
Rtype
Ori

Memory

32

Mux

Ideal
Memory

Rt

Control

Op

Func

6
6

Imm
16

Extend

ExtOp=1

32

0
1
2
3

Target
Zero

ALU

RAdr

Rs

32

Mux

Mux

32

Instruction Reg

32
32

Mux

IorD=x MemWr=0
IRWr=0RegDst=xRegWr=0ALUSelA=0

BrWr=1

32
32

ALU
Control

ALUSelB=10
32

ALUOp=Add

17

Branch Completion: Cycle 3

BrComplete

if (busA == busB)
PC <- Target

ALUOp=Sub
ALUSelB=01
x: IorD, Mem2Reg
RegDst, ExtOp
1: PCWrCond
ALUSelA
PCSrc

PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Rd

Ra
Rb

busA

Reg File
Rw
busW

busB

32
32

<< 2
Imm
16

Extend

ExtOp=x

32

0
1
2
3

Zero

ALU

Rs

Mux

Ideal
Memory

Mux

RAdr

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=1
PCSrc=1 BrWr=0
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=xRegWr=0 ALUSelA=1 1
32

32
32

ALU
Control

ALUSelB=01
32

ALUOp=Sub
18

Multiple Cycle Implementation of R-type

Instructions

19

R-Type Instruction Decode: Cycle 2

Next Cycle: R-type Execution

PCWr=0

PCWrCond=0
PCSrc=x BrWr=1
Zero
Target
IorD=x MemWr=0IRWr=0 RegDst=x RegWr=0 ALUSelA=0 1

PC

WrAdr
32
Din Dout

32
32

Beq
Rtype
Ori
Memory

32

Rt
Rt 0

Rd

Ra
Rb

busA

Reg File
Rw
busW busB

32

<< 2
Control

Op

Func

6
6

Imm
16

Extend

ExtOp=1

32

1
32

Zero

ALU

Rs

Mux

Ideal
Memory

Mux

32

RAdr

Mux

32

Instruction Reg

32
0

32

Mux

32

0
1
2
3

32
32

ALU
Control

ALUSelB=10
32

ALUOp=Add

20

R-type Execution: Cycle RExec

3

1: RegDst
ALUSelA
ALUSelB=01
ALUOp=Rtype
x: PCSrc, IorD
MemtoReg
ExtOp

ALU Output <- busA op busB

PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb busA

Reg File

32

Rw

busB
busW
32

Ra

Mux 0

<< 2

Extend

ExtOp=x

32

0
1
2
3

Zero

ALU

RAdr

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x BrWr=0
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=1RegWr=0 ALUSelA=1 1
32

32
32

ALU
Control

32

ALUOp=Rtype
MemtoReg=x
ALUSelB=01
21

R-type Completion: Cycle 4

Rfinish

R[rd] <- ALU Output

ALUOp=Rtype
1: RegDst, RegWr
ALUselA
ALUSelB=01
x: IorD, PCSrc
ExtOp

PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb

busA

Reg File

32

Rw
busWbusB 32

Ra

Mux 0

<< 2

Extend

ExtOp=x

32

32

0
1
2
3

Zero

ALU

RAdr

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x BrWr=0
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=1RegWr=1 ALUSelA=1 1
32

32
32

ALU
Control

ALUOp=Rtype
22
MemtoReg=0
ALUSelB=01

Multiple Cycle Implementation of Or

Immediate

23

Ori Instruction Decode: Cycle 2

Next Cycle: Ori Execution
PCWr=0

Mux

PCWrCond=0
PCSrc=x BrWr=1
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=xRegWr=0 ALUSelA=0 1
32
32

PC

WrAdr
32
Din Dout

32
32

Beq
Rtype
Ori
Memory

32

Rt

Rt 0

Rd

Ra
Rb

busA

Reg File

32

Rw
busWbusB 32

<< 2
Control

Op

Func

6
6

Imm
16

Extend

ExtOp=1

32

0
1
2
3

Zero

ALU

Rs

Mux

Ideal
Memory

Mux

32

RAdr

Mux

32

Intruction Reg

32

32
32

ALU
Control

ALUSelB=10
32

ALUOp=Add
24

Ori Execution: Cycle 3

ALUOp=OrOriExec
1: ALUSelA

ALU output <- busA or ZeroExt[Imm16]

ALUSelB=11
x: MemtoReg
IorD, PCSrc

PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb

busA

Reg File

32

Rw
busWbusB 32

Ra

Mux 0

<< 2

Extend

ExtOp=0

32

32

0
1
2
3

Zero

ALU

RAdr

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x BrWr=0
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=0RegWr=0 ALUSelA=1 1
32

32
32

ALU
Control

ALUOp=Or
25
MemtoReg=x
ALUSelB=11

Ori Completion: Cycle 4OriFinish

ALUOp=Or

Reg[rt] <- ALU output

PCWr=0

x: IorD, PCSrc
ALUSelB=11
1: ALUSelA
RegWr

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb

busA

Reg File

32

Rw
busWbusB 32

Ra

Mux 0

<< 2

Extend

ExtOp=0

32

32

0
1
2
3

Zero

ALU

RAdr

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x BrWr=0
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=0RegWr=1 ALUSelA=1 1
32

32
32

ALU
Control

ALUOp=Or
26
MemtoReg=0
ALUSelB=11

Multiple Cycle Implementation of Load

and Store

27

Instruction Decode: Cycle 2

Next Cycle: Memory Address Calculation

PCWr=0

Mux

PCWrCond=0
PCSrc=x BrWr=1
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=xRegWr=0 ALUSelA=0 1
32
32

PC

WrAdr
32
Din Dout

32
32

Beq
Rtype
Ori
Memory

32

Rt

Rt 0

Rd

Ra
Rb

busA

Reg File

32

Rw
busWbusB 32

<< 2
Control

Op

Func

6
6

Imm
16

Extend

ExtOp=1

32

0
1
2
3

Zero

ALU

Rs

Mux

Ideal
Memory

Mux

32

RAdr

Mux

32

Instruction Reg

32

32
32

ALU
Control

ALUSelB=10
32

ALUOp=Add
28

Memory Address
Calculation
Cycle 3

AdrCal

1: ExtOp
ALUSelA
ALUSelB=11
ALUOp=Add
x: MemtoReg
PCSrc

ALU output <- busA +

SignExt[Imm16]
PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb

busA

Reg File

32

Rw
busWbusB 32

Ra

Mux 0

<< 2

Extend

ExtOp=1

32

32

0
1
2
3

Zero

ALU

RAdr

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x BrWr=0
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=xRegWr=1 ALUSelA=1 1
32

32
32

ALU
Control

ALUOp=Add
29
MemtoReg=x
ALUSelB=11

Memory Access for

Store
Cycle 4

mem[ALU output] <- busB

PCWr=0

1: ExtOp SWmem
MemWr
ALUSelA
ALUSelB=11
ALUOp=Add
x: PCSrc,RegDst
MemtoReg
PCSrc=x

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb

busA

Reg File

32

R
w
busWbusB 32

Ra

Mux 0

<< 2

Extend

ExtOp=1

32

32

32

0
1
2
3

Target
Zero

ALU

RAdr

1
0

Mux

32

Mux

32

Instruction Reg

32

BrWr=0

Mux

PCWrCond=0
Zero
IorD=xMemWr=1IRWr=0RegDst=xRegWr=0 ALUSelA=1

32
32

ALU
Control

ALUOp=Add
30
MemtoReg=x
ALUSelB=11

Memory Access for

Load
Cycle 4

1: ExtOp LWmem
ALUSelA, IorD
ALUSelB=11
ALUOp=Add
x: MemtoReg
PCSrc

Mem Dout <- mem[ALU output]

PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb

busA

Reg File

32

Rw
busWbusB 32

Ra

Mux 0

<< 2

Extend

ExtOp=1

32

32

0
1
2
3

Zero

ALU

RAdr

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x BrWr=0
Zero
Target
IorD=1MemWr=0IRWr=0RegDst=0RegWr=0 ALUSelA=1 1
32

32
32

ALU
Control

ALUOp=Add
31
MemtoReg=x
ALUSelB=11

Write Back for

Load
Cycle 5

LWwr

1: ALUSelA
RegWr, ExtOp
MemtoReg
ALUSelB=11
ALUOp=Add
x: PCSrc
IorD

Reg[rt] <- Mem Dout

PCWr=0

32

PC

WrAdr
32
Din Dout

32
32

32

Rt

Rt 0

Mux

Ideal
Memory

Rs

Rd

Imm 16

Rb

busA

Reg File

32

Rw
busWbusB 32

Ra

Mux 0

<< 2

Extend

ExtOp=1

32

32

0
1
2
3

Zero

ALU

RAdr

Mux

Mux

32

Instruction Reg

32
32

Mux

PCWrCond=0
PCSrc=x BrWr=0
Zero
Target
IorD=xMemWr=0IRWr=0RegDst=0RegWr=0 ALUSelA=1 1
32

32
32

ALU
Control

ALUOp=Add
32
MemtoReg=1
ALUSelB=11

Putting It All Together

33

Putting it all together: Multiple Cycle

Datapath
PCWr

RegWr

ALUSelA

WrAdr
32
Din Dout

32
32

32

Rt 0

Mux

Ideal
Memory

Rt

Rd

Imm 16

Rb

busA

Reg File

32

Rw

Mux 0

<< 2

Extend

ExtOp

32

busWbusB 32

Ra

0
1
2
3

Zero

32
32

ALU
Control

32

MemtoReg

Target

ALU

RAdr

32

Rs

BrWr

Mux

Mux

Instruction Reg

32

32

RegDst

32

PC
32

PCSrc

Mux

PCWrCond
Zero
IorD MemWr IRWr

ALUSelB

ALUOp34

Putting it all together: Control State Diagram

Ifetch
AdrCal

1: ExtOp
ALUSelA
ALUSelB=11
ALUOp=Add
x: MemtoReg
PCSrc

lw

ALUOp=Add
1: PCWr, IRWr
x: PCWrCond
RegDst, Mem2R
Others: 0s

lw or sw
sw
SWMem

1: ExtOp LWmem
ALUSelA, IorD
1: ExtOp
MemWr
ALUSelB=11
ALUSelA
ALUOp=Add
ALUSelB=11
x: MemtoReg
ALUOp=Add
PCSrc
x: PCSrc,RegDst
MemtoReg

LWwr

1: ALUSelA
RegWr, ExtOp
MemtoReg
ALUSelB=11
ALUOp=Add
x: PCSrc
IorD

Rfetch/Decode
ALUOp=Add
1: BrWr, ExtOp
ALUSelB=10
x: RegDst, PCSrc
IorD, MemtoReg
Others: 0s

beq

Ori
Rtype
RExec 1: RegDst
ALUSelA
ALUSelB=01
ALUOp=Rtype
x: PCSrc, IorD
MemtoReg
ExtOp

Rfinish

ALUOp=Rtype
1: RegDst, RegWr
ALUselA
ALUSelB=01
x: IorD, PCSrc
ExtOp

BrComplete
ALUOp=Sub
ALUSelB=01
x: IorD, Mem2Reg
RegDst, ExtOp
1: PCWrCond
ALUSelA
PCSrc

OriExec
ALUOp=Or
1: ALUSelA
ALUSelB=11
x: MemtoReg
IorD, PCSrc

OriFinish
ALUOp=Or
x: IorD, PCSrc
ALUSelB=11
1: ALUSelA
RegWr
35