Advanced RISC Machine(ARM) was developed by the Acorn Company.

ARM is intended for applications that require power efficient processors such as
portable computer, smart card, data communication etc..
ARM uses two types of instructions called Thumb(16-bit instructions) and
Thumb-2(32-bit instructions).
ARM is a load store reducing instruction set computer architecture
i.e core cannot directly operate with the memory

Block Diagram of ARM7 architecture:

Block Diagram of Cortex-M3:

ARM uses 7 processing modes that are used to run the user tasks
User: for normal operations
IRQ: for handling interrupt operations
FIQ: for fast interrupt mode
Supervisory: used by operating system
Undefined: when undefined instruction executes
Abort: this mode indicates that current memroy access cannot be
completed such as unavailability of data in memory
User Vs System: Most applications perform in user mode and hence there
is no availability of system resources, other than causing an exception to
occur. This allows a customized OS to control the use of resources. System
mode, it is intended for use by OS tasks that need access to system
resources not depending upon exceptions.

ARM Nomenclature:
There are different versions of ARM, like ARMTDMI, ARM10XE, the meaning of
TDMI and XE is given below:
ARM {X} {Y} {Z} {T} {D} {M} {I} {E} {J} {F} {S}
X Family
Y Memory management
Z Cache
T THUMB 16-bit decoder
D JTAG Debug
M Fast multiplier
I Embedded ICE macro cell
E Enhanced Instruction
J Jazelle (Java)
F Vector floating point unit
S Synthesizable version

ARM 7 processor has total of 37 registers: 31 general-purpose

registers(including PC) and 6 status registers. All are 32-bit wide.
At any time, 15 GPRs(R0-R14), one or two status registers and the PC are
visible.

Fig: Register Description of ARM7TDMI in different modes

At User mode, only 16 registers (R0-R15) and one Program Status Register
are available to programmers.
Out of which: R15 PC
R14 Link Register
R13 SP
Note: link register is also a special purpose register which holds the address to
return to when a function call completes. Hence the name, Sub-Routine
Link Register.
Program Status Registers:
Current Program Status Register (CPSR) and Saved Program Status Register
(SPSR)
*** SPSR is the exact replica of CPSR. Used only while exceptions. ****
CPSR is accessible in all processor modes. Showed in fig below.
Every exception mode has SPSR, which is used to preserve the value of the
CPSR when the associated exception occurs.

Condition Code Flags:

> N: For signed integer twos complement, N=1 if result is Negative
N=0 if it is Positive or Zero
> Z: This bit is Set, if the result of the instruction is Zero (also indicates
equal in some instructions)
> C: This bit behavior changed based on the instruction used. C=1 in an
addition if produced a carry; C=0 in a subtraction produced a borrow; C=last
bit shifted out of the value produced in a shift operation.
> V: Overflow occurs
> Q: In E variants of ARMv5 and above, Q flag is used to indicate whether
overflow has occurred in some DSP oriented instructions. In other variants,
this bit in CPSR is treated as reserved bit.
> GE[3:0]: In ARMv6 and above these bits are used as Greater than or
Equal(GE) flag for every byte of the result. Prior to ARMv6, this bit is treated
as reserved bit.
> E: Load and store Endianness for data handling. Prior to ARMv6, this bit is
treated as reserved bit.
Interrupt Disable Bits (A, I, F):
> I: Disables IRQ interrupts when it is set
> F: Disables FIQ interrupts when it is set

Mode bits (M[4:0]): These bits determine the mode processor is operating

T & J bits:

Core registers of Cortex-M3:

Processor Modes of Cortex-M3: Thread Mode and Handler Mode

Thread Mode: Executes application s/w. Processor will be in thread mode
when it comes out of RESET.
Handler Mode: Used to handle exceptions. Processor again returns to
thread mode when it finishes processing of all exceptions.
Note: Processor while executing any s/w, will assign some Privilege levels
to it.
**Privilege means accessing all instructions, all registers, all system
resources, some times even memory
Privilege levels in cortex-m3 are: Unprivileged and Privileged
In Unprivileged, the s/w cannot use CPS instruction, and limited access to
MSR & MRS instructions. s/w cannot access the system timer, NVIC and
also s/w might have restricted access to memory or peripherals
In Privileged, s/w can use all the instructions and has all access to
resources.
Note: In Handler mode, s/w execution is always privileged. Where as in
Thread mode, the control register controls whether the s/w execution is
privileged or unprivileged.

R0 R7: are called Low Registers. These can be accessed by both 16-bit
Thumb Instructions and 32-bit Thumb2 Instructions
R8 - R12: are called High Registers. These can be accessed only by 32-bit
Thumb2 Instructions but not 16-bit Thumb Instructions
R13(SP): In cortex-M3 there are two SPs. Main Stack and the Processor
Stack. Used for stack operations in each mode. In Thread mode, bit1 of
control register controls which stack register is used. In Handler mode, the
processor always uses the main stack.

R14(LR): used while dealing with sub-routines

R15(PC):

TheProgram Status Register(PSR) combines:

Application Program Status Register(APSR) + Interrupt Program Status
Register(IPSR) + Execution Program Status Register(EPSR)
These registers are mutually exclusive bit fields in the 32-bit PSR.

Can access these registers individually or can be accessed as a whole PSR

register using the instructions MSR or MRS
MRS means system register to general purpose register. Syntax is MRS
Rd, PSR
MSR means general purpose register to system register. Syntax is MSR
system register, Rn
APSR: contains the current state of condiiton flags.

IPSR: contains the exception type number of the current ISR

where n in the range of 1-240

EPSR: contains the Thumb state bit (T) and the execution state bits for either IT
(If-Then)instruction or ICI(Interruptible-Continuable Instructions) instructions.
This EPSR is only effected when dealing with ICI related instructions(LDM,
STM, PUSH, POP) and IT instruction.

Exception Mask Registers: Priority mask register(PRIMASK); Fault Mask

Register(FAULTMASK); Base Priority Mask Register(BASEPRI)
PRIMASK Register:

if 0th bit is 1- prevents the activation of all exceptions with priority

0- No effect
FAULTMASK Register:

If 0th bit is 1- prevents the activation of all exceptions except for NMI.
0- No effect

BASEPRI Register:

Bits 0 to 7: If not zero, then it defines the base priority for exception
processing.
If zero, no effect.

Control Register:

Instruction Set Architecture:

Each CPU has a known instruction set that a programmer can use to write
assembly language programs.
Classification of Instructions based on number of operands:
> No Operand Instructions: instructions which has only mnemonic and no
operands.
Eg: HLT, NOP
> One Operand Instructions: Instructions which has a mnemonic and only
one operand
Eg: INC R1
DEC R1
J target ; Jump to memory location labelled by target
> Two Operand Instructions:
Eg: ADD R1, R2 ; R1=R1+R2
> Three Operand Instructions:
Eg: ADD R1, R2, R3
; R1=R2+R3

Note: Most modern processors use instructions with three operands.

Data Processing Instructions:

mnemonic {cond} {s} Rd, Rn(i.e operand1), operand2
Note: commands inside {} are optional.
mnemonic: ADD, SUB etc..
{s}: means update the PSR flag bits
{cond}: means the instruction will be executed if meet the conditions
Rd: Destination Register
Rn: Operand1
Operand2: can be a register or an immediate value

Cortex Microcontroller Software Interface Standard (CMSIS):

In Cortex-M3 microcontroller systems, CMSIS defines:
the names of core peripherals and the way to access their registers;
defines exception vectors and the names of the exception vectors;
and interface for RTOS kernel.
CMSIS includes address definitions and data structures for the peripherals.

AMBA (Advanced Microcontroller Bus Architecture): is an on-chip

interconnect specification standard. AMBA is a registered trademark of
ARM ltd.
Introduce by ARM in 1996
Hierarchy of the versions are AMBA, AMBA2, AMBA3, AMBA4, AMBA5
ARM7, ARM9, ARM Cortex-M uses AMBA2 specifications
AMBA2 consists of AHB (Advanced High-performance Bus) or ASB
(Advanced System Bus) and APB (Advanced Peripheral Bus)
AHB-Lite is a subset of AHB which simplified the design consists of a bus
with a single master
AHB is mainly intended for high-performance, high-clock frequency
systems which implements burst transfers, split transaction, single-clock
edge operations
APB is intended for interfacing peripherals which have memory-mapped
registers, have no high-bandwidth interfaces, are accessed under program
control