PIC MICROCONTROLLER

UNIT III
Mr. S. VINOD
ASSISTANT PROFESSOR
EEE DEPARTMENT

Architecture
memory organization
addressing modes
instruction set
PIC programming in Assembly &
C
I/O port
Data Conversion
RAM & ROM Allocation
Timer programming

PIC18F Microcontrollers
Microcontroller Unit (MCU)
Microprocessor unit (MPU)
Harvard Architecture
Program memory for instructions
Data memory for data

I/O ports
Support devices such as timers

Microcontroller Unit

PIC18F MPU and Memory

Microprocessor Unit
Includes Arithmetic Logic Unit (ALU),
Registers, and Control Unit
Arithmetic Logic Unit (ALU)
Instruction decoder
16-bit instructions

Status register that stores flags

5-bits

WREG working register

8-bit accumulator

Microprocessor Unit
Registers
Program Counter (PC)
21-bit register that holds the Program Memory address

Bank Select Register (BSR)

4-bit register used in direct addressing the Data
Memory

File Select Registers (FSRs)

12-bit registers used as memory pointers in indirect
addressing Data Memory

Control unit
Provides timing and control signals
Read and Write operations
7

PIC18F - Address Buses

Address bus
21-bit address bus for Program Memory
Addressing capacity: 2 MB

12-bit address bus for Data Memory

Addressing capacity: 4 KB

Data Bus and Control

Signals
Data bus
16-bit instruction/data bus for Program
Memory
8-bit data bus for Data Memory

Control signals
Read and Write

PIC18F452/4520 Memory
Program Memory: 32 K
Address range: 000000 to 007FFFH

Data Memory: 4 K
Address range: 000 to FFFH

Data EEPROM
Not part of the data memory space
Addressed through special function
registers
10

PIC18F452/4520 Memory
Program Memory

Data Memory

11

Data Memory Banks

12

PIC18F452 I/O Ports

Five I/O ports
PORT A through PORT E
Most I/O pins are multiplexed
Generally have eight I/O pins
Addresses already assigned to these
ports
Each port is identified by its assigned
SFR

13

I/O Ports A and B

14

Data Transfer

15

MCU Support Devices

Timers
Capture, Compare and PWM (CCP
Modules)

Serial Communications
Master Synchronous Serial Port (MSSP)
Addressable USART

A/D converter
Parallel Slave Port (PSP)
Data EEPROM
16

MCU Support Devices

17

PIC18F Special Features

Sleep mode
Watchdog timer (WDT)
Code protection
In-circuit serial programming
In-circuit debugger

330_02

18

PIC18F4X2 Architecture Block Diagram

PIC18F452 Programming
Model

330_02

20

dual in-linepackage
Quad FlatPackage

The PIC18 Memory Organization

Data Memory and Program Memory are separated
Separation of data memory and program memory
makes possible the simultaneous access of data
and instruction.
Data memory are used as general-purpose
registers or special function registers
On-chip Data EEPROM are provided in some PIC18
MCUs

Separation of Data Memory and Program Memory

PIC18 Data Memory

Implemented in SRAM and consists of generalpurpose
registers
and
special-function
registers. Both are referred to as data registers.
A PIC 18 MCU may have up to 4096 bytes of
data memory.
Data memory is divided into banks. Each bank
has 256 bytes.
General-purpose registers are used to hold
dynamic data.
Special-function registers are used to control
the operation of peripheral functions.

PIC18 Data Memory

Only one bank is active at any time. The active
bank is specified by the BSR register.
Bank switching is an overhead and can be errorprone
PIC18 implements the access bank to reduce the
problem caused by bank switching.
Access bank consists of the lowest 96 bytes and
the highest 160 bytes of the data memory space.

Data memory map for PIC18 devices

Program Memory Organization

The program counter (PC) is 21-bit long,
which enables the user program to
access up to 2 MB of program memory.
The PIC18 has a 31-entry return address
stack to hold the return address for
subroutine call.
After power-on, the PIC18 starts to
execute instructions from address 0.
The location at address 0x08 is reserved
for high-priority interrupt service routine.

Program Memory Organization

The location at address 0x18 is reserved
for low-priority interrupt service priority
interrupt service routine.
Up to 128KB (at present time) of
program memory is inside the MCU chip.
Part of the program memory is located
outside of the MCU chip.

P ro gra m
memory
Organizatio
n

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are
registers used by the CPU and peripheral
modules for controlling the desired
operation of the device.
These registers are implemented as static
RAM in the data memory space.
SFRs start at the top of data memory and
extend downward to occupy the top
segment of Bank 15, from F60h to FFFh.
The SFRs can be classified into two sets:
those associated with the core device
functionality (ALU, Resets and interrupts)
and those related to the peripheral

The PIC18 CPU Register

The group of registers from 0xFD8 to
0xFFF are dedicated to the general
control of MCU operation.
The CPU registers
The WREG register is involved in the
execution of many instructions.
The STATUS register holds the status
flags for the instruction execution.

Addr Nam
ess e

explanation

FFFh

TOSU

Top-of-Stack UPPER (20-16)

FFEh

TOSH

Top-of-Stack HIGHER(15-8)

FFDh

TOSL

Top-of-Stack LOWER(7-0)

FFCh

STKPTR

Return address stack pointer (STKFUL STKUNF)

FFBh

PCLATU

Holding Register for PC(20-16)

FFAh

PCLATH

Holding Register for PC(15-8)

FF9h

PCL

Holding Register for PC(7-0)

FF8h

TBLPTRU

Program Memory Table Pointer Upper Byte

(Access fixed data residing in the program ROM
space) (20-16)

FF7h

TBLPTRH

Program Memory Table Pointer High Byte (15-8)

FF6h

TBLPTRL

Program Memory Table Pointer Low Byte(7-0)

FF5h

TABLAT

Program Memory Table Latch

FF4h

PRODH

Product Register High Byte

FF3h

PRODL

Product Register Low Byte

Addr Nam
ess e

explanation

FF2

INTCON

INTurrptCONtrol register

FF1

INTCON2

INTERRUPT CONTROL REGISTER2

FF0

INTCON3

INTERRUPT CONTROL REGISTER 3

FEF

INDF0

FEE

POSTINC
0

FED

POSTDEC
0

FEC

PREINC0

FEB

PLUSW0

FEA

FSR0H

Indirect Data Memory Address Pointer 0 High

Byte

FE9

FSR0L

Indirect Data Memory Address Pointer 0 lower

Byte

FE8

WREG

Working Register

FE7

INDF1

FSR
o

Addr Nam
ess e

explanation

FE5

POSTDEC
1

FE4

PREINC1

FE3

PLUSW1

FE2

FSR1H

Indirect Data Memory Address Pointer 1 High

Byte

FE1

FSR1L

Indirect Data Memory Address Pointer 1 lower

Byte

FE0

BSR

FDF

INDF2

FDE

POSTINC
2

FDD

POSTDEC
2

FDC

PREINC2

FDB

PLUSW2

Addr Nam
ess e
FD8

STATUS

explanation

STATUS register

PIC18 Pipelining
The PIC18 Divide most of the instruction
execution into two stages: instruction fetch
and instruction execution.
Up to two instructions are overlapped in their
execution One instruction is in Up to two
instructions are overlapped in their execution.
One instruction is infetch stage while the
second instruction is in execution stage.
Because of pipelining, each instruction
appears to take one instruction cycle to
complete.

PIC18 Pipelining

Introduction to PIC18 Instruction Set

Includes 77 instructions; 73 one word (16-bit)
long and remaining four two words (32-bit)
long
Divided into seven groups

Move (Data Copy) and Load

Arithmetic
Logic
Program Redirection (Branch/Jump)
Bit Manipulation
Table Read/Write
Machine Control

Move and Load Instructions

MOVLW
MOVLW

8-bit
0 x F2

MOVWF

F, a
;Copy WREG in File (Data) Reg.
; If a = 0, F is in Access Bank
;If a = 1, Bank is specified by BSR
0x25, 0 ;Copy W in Data Reg.25H

MOVWF

;Load an 8-bit literal in WREG

MOVFF fs, fd
;Copy from one Data Reg. to
;another Data Reg.
MOVFF 0x20,0x30
;Copy Data Reg. 20 into Reg.30

Arithmetic Instructions
ADDLW 8-bit
ADDLW 0x32

;Add 8-bit number to WREG

;Add 32H to WREG

ADDWF F, d, a ;Add WREG to File (Data) Reg.

;Save result in W if d =0
;Save result in F if d = 1
ADDWF 0x20, 1;Add WREG to REG20 and
;save result in REG20
ADDWF 0x20, 0;Add WREG to REG20 and
;save result in WREG

(1 of 3)

Arithmetic Instructions

(2 of 3)

ADDWFC F, d, a
;Add WREG to File Reg. with
;Carry and save result in W or F
SUBLW
8-bit
;Subtract WREG from literal
SUBWF
F, d, a
;Subtract WREG from File Reg.
SUBWFB F, d, a
;Subtract WREG from File Reg.
;with Borrow
INCF F, d, a
;Increment File Reg.
DECF F, d, a
;Decrement File Reg.
COMF F, d, a
;Complement File Reg.
NEGF F, a
;Take 2s Complement-File Reg.

Arithmetic Instructions
MULLW

(3 of 3)

8-bit ;Multiply 8-bit and WREG

;Save result in PRODH-PRODL
MULWF F, a ;Multiply WREG and File Reg.
;Save result in PRODH-PRODL
DAW
;Decimal adjust WREG for BCD
;Operations

Logic Instructions
ANDLW
ANDWF

8-bit
;AND literal with WREG
F, d, a
;AND WREG with File Reg. and
;save result in WREG/ File Reg.

IORLW 8-bit
;Inclusive OR literal with WREG
IORWF F, d, a
;Inclusive OR WREG with File Reg.
;and save result in WREG/File Reg.
XORLW
XORWF

8-bit
;Exclusive OR literal with WREG
F, d, a
;Exclusive OR WREG with File Reg.
;and save result in WREG/File Reg.

Branch Instructions

BC
n
;Branch if C flag = 1 within + or 64 Words
BNC n ;Branch if C flag = 0 within + or 64 Words
BZ
n
;Branch if Z flag = 1 within + or 64 Words
BNZ n ;Branch if Z flag = 0 within + or 64 Words
BN
n ;Branch if N flag = 1 within + or 64 Words
BNN n ;Branch if N flag = 0 within + or 64 Words
BOV n ;Branch if OV flag = 1 within + or 64 Words
BNOV n ;Branch if OV flag = 0 within + or 64 Words
GOTO Address: Branch to 20-bit address unconditionally

Call and Return Instructions

RCALL nn ;Call subroutine within +or 512 words
CALL 20-bit, s ;Call subroutine
;If s = 1, save W, STATUS, and BSR
RETURN, s
;Return subroutine

;If s = 1, retrieve W, STATUS, and BSR

RETFIE, s
;Return from interrupt

;If s = 1, retrieve W, STATUS, and BSR

Bit Manipulation Instructions

BCF F, b, a ;Clear bit b of file register.
b = 0 to 7
BSF F, b, a ;Set bit b of file register.
b = 0 to 7
BTG F, b, a ;Toggle bit b of file register.
b = 0 to 7
RLCF F, d, a ;Rotate bits left in file register through
; carry and save in W or F register
RLNCF F, d, a
;Rotate bits left in file register
; and save in W or F register
RRCF F, d, a ;Rotate bits right in file register through

; carry and save in W or F register

RRNCF F, d, a ;Rotate bits right in file register
; and save in W or F register

Test and Skip Instructions

BTFSC F, b, a ;Test bit b in file register and
skip the
;next instruction if bit is
cleared (b =0)
BTFSS F, b, a ;Test bit b in file register and
skip the
;next instruction if bit is set
(b =1)
CPFSEQ F, a ;Compare F with W, skip if F = W
CPFSGT F, a ;Compare F with W, skip if F > W
CPFSLT F, a ;Compare F with W, skip if F < W
TSTFSZ F, a ;Test F; skip if F = 0

Increment/Decrement
and Skip Next Instruction

DECFSZ F, b, a ;Decrement file register and

skip the
;next instruction if F = 0
DECFSNZ F, b, a ;Decrement file register and
skip the
;next instruction if F 0
INCFSZ F, b, a ;Increment file register and skip
the
;next instruction if F = 0
INCFSNZ F, b, a ;Increment file register and skip
the
;next instruction if F 0

Table Read/Write
Instructions (1 of 2)
TBLRD* ;Read Program Memory pointed by TBLPTR
;into TABLAT
TBLRD*+ ;Read Program Memory pointed by TBLPTR
;into TABLAT and increment TBLPTR
TBLRD*- ;Read Program Memory pointed by TBLPTR
;into TABLAT and decrement TBLPTR
TBLRD+* ; Increment TBLPTR and Read Program
; Memory pointed by TBLPTR into TABLAT

Table Read/Write
Instructions (2 of 2)
TBLWT* ;Write TABLAT into Program Memory
pointed
;by TBLPTR
TBLWT*+ ; Write TABLAT into Program Memory
pointed
;by TBLPTR and increment TBLPTR
TBLWT*- ; Write TABLAT into Program Memory
pointed
;by TBLPTR and decrement TBLPTR
TBLWT+* ; Increment TBLPTR and Write TABLAT
into
; Program Memory pointed by TBLPTR

Instruction Format

(1 of 3)

The PIC18F instruction format divided

into four groups
Byte-Oriented operations
Bit-Oriented operations
Literal operations
Branch operations

Execution of an Instruction
Instruction: MOVLW 0x37 ; Load
37H in W
Memory
Address

Hex
Code

000020
000021

37
0E

Mnemonics

MOVLW 0x37

PIC18 Addressing Modes

PIC18 Addressing Modes

I/O PORTS
Depending on the device selected and
features enabled, there are up to five ports
available. Some pins of the I/O ports are
multiplexed with an alternate function from the
peripheral features on the device. In general,
when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation.
These registers are:
TRIS register (data direction register)
PORT register (reads the levels on the pins of the
device)
LAT register (output latch)

GENERIC I/O PORT OPERATION

PORTA, TRISA and LATA Registers

PORTA is an 8-bit wide, bidirectional port.
The corresponding data direction register is
TRISA. Setting a TRISA bit (= 1) will make
the corresponding PORTA pin an input.
Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output.
Reading the PORTA register reads the status
of the pins; writing to it will write to the port
latch.
Read-modify-write operations on the LATA
register read and write the latched output
value for PORTA.

PORTA I/O SUMMARY

PORTA I/O SUMMARY

INITIALIZING PORTA

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

PORT B

PORT B

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

SUMMARY OF REGISTERS ASSOCIATED WITH

PORTD

SUMMARY OF REGISTERS ASSOCIATED

WITH PORTE

Assembly Language Program Structure

A program written in assembly language consists
of a sequence of statements that tell the computer
to perform the desired operations. From a global
point of view, a PIC18 assembly program consists of
three types of statements:
Assembler directives. Assembler directives are assembler commands
that are used
to control the assembler: its input, output, and data allocation. An
assembly
program must be terminated with an END directive. Any statement after
the END
directive will be ignored by the assembler.
Assembly language instructions. These instructions are PIC18
instructions. Some
are defined with labels. The PIC18 MCU allows us to use up to 77 different
instructions.

LED (turn ON and turn OFF)

;*****Set up the Constants****
STATUS equ 03h ;
TRISA equ 85h ;
PORTA equ 05h ;
COUNT1 equ 08h ;
COUNT2 equ 09h ;

Address of the STATUS register

Address of the tristate register for port A
Address of Port A
First counter for our delay loops
Second counter for our delay loops

;****Set up the port****

bsf STATUS,5 ;
movlw 00h ;
movwf TRISA ;
bcf STATUS,5 ;

Switch to Bank 1
Set the Port A pins
to output.
Switch back to Bank 0

;****Turn the LED on****

Start movlw 02h ;
Turn the LED on by first putting
movwf PORTA ;
it into the w register and then
on the port

;****Start of the delay loop 1****

Loop1

decfsz COUNT1,1 ;
Subtract 1 from 255
goto Loop1 ;
If COUNT is zero, carry on.
decfsz COUNT2,1 ;
Subtract 1 from 255
goto Loop1 ;
Go back to the start of our
loop. This delay counts
down from 255 to
zero,
255 times
;****Delay finished, now turn the LED off****
movlw 00h ;
Turn the LED off by first putting
movwf PORTA ;
it into the w register and then on
the port
;****Add another delay****
Loop2 decfsz COUNT1,1 ; This second loop keeps the
goto Loop2 ;
LED turned off long enough for
decfsz COUNT2,1 ;
us to see it turned off
goto Loop2 ;
;****Now go back to the start of the program
goto Start ;
go back to Start and turn LED on again
;****End of the program****
end

DATA TYPE CONVERSION

The main data types are put in hierarchical order as follows:

If two operands of different type are used in an arithmetic operation, the lower
priority operand type is automatically converted into the higher priority operand
type.
If the highest priority operand is of typedouble, then types of all other operands
in the expression as well as the result are automatically converted into
typedouble.
If the highest priority operand is of typelong, then types of all other operands in
the expression as well as the result are automatically converted into typelong.
If the operands are oflongorchartype, then types of all other operands in the
expression as well as the result are automatically converted into typeint.

MPLAB IDE

What is IDE?
Integrated
Development
Environment (IDE)
Collection of
integrated
programs (tools) to
write assembly
programs,
assemble, execute,
and debug
programs.
Microchip IDE is
called MPLAB IDE

Writing Assembly Programs /

and IDE Structure

File Structure in IDE

Project_name.mcp
Project_name.mcw
Project_name.mcs
code_listing.asm

New project

Code listing

Error File (.err)

Error[113] C:\MCC18\CLASS_PROJECT\ADDCARY.ASM 9 : Symbol

not previously defined (START)
Error[122] C:\MCC18\CLASS_PROJECT\ADDCARY.ASM 11 : Illegal
opcode (MOViLW)
Warning[207] C:\MCC18\CLASS_PROJECT\ADDCARY.ASM 17 : Found
label after column 1. (MOiVLW)
Error[108] C:\MCC18\CLASS_PROJECT\ADDCARY.ASM 17 : Illegal
character (0)

Line Number which

has an error. Read
the error and
correct it.

List file (*.lst)

000000 EF10 F000
00009
GOTO START
000020
00010
ORG
0020H
000020 0EF2
00011 START: MOVLW BYTE1
000022 6E00
00012
MOVWF REG0,0
000024 0E32
00013
MOVLW BYTE2
000026 6E01
00014
MOVWF REG1,0
000028 2400
00015
ADDWF REG0,0,0
00002A E301
00016
BNC
SAVE
00002C 0E00
00017
MOVLW 0x00
00002E 6E02
00018 SAVE: MOVWF REG2,0
000030 0003
00019
SLEEP
00020
END
MPASM 5.12
ADDCARY.ASM 2-26-2008 20:03:03
PAGE 2

MEMORY USAGE MAP ('X' = Used, '-' = Unused)

0000 : XXXX------------ ---------------- XXXXXXXXXXXXXXXX
XX-------------All other memory blocks unused.

SYMBOL TABLE
LABEL
BYTE1
BYTE2
REG0
REG1
REG2
SAVE
START
__18F452
Messages :

VALUE
000000F2
00000032
00000000
00000001
00000002
0000002E
00000020
00000001

0 reported,

0 suppressed

Program Memory Bytes Used: 22

Program Memory Bytes Free: 32746
Errors :
0
Warnings :
0 reported,

0 suppressed

Identifies all memory

locations and opcodes
in the source code

List file (*.lst)

Memory
Address

000000 EF10 F000

00009
GOTO START
000020
00010
ORG
0020H
000020 0EF2
00011 START: MOVLW BYTE1
000022 6E00
00012
MOVWF REG0,0
000024 0E32
00013
MOVLW BYTE2
000026 6E01
00014
MOVWF REG1,0
000028 2400
00015
ADDWF REG0,0,0
00002A E301
00016
BNC
SAVE
00002C 0E00
00017
MOVLW 0x00
00002E 6E02
00018 SAVE: MOVWF REG2,0
000030 0003
00019
SLEEP
00020
END
MPASM 5.12
ADDCARY.ASM 2-26-2008 20:03:03
PAGE 2

MEMORY USAGE MAP ('X' = Used, '-' = Unused)

0000 : XXXX------------ ---------------- XXXXXXXXXXXXXXXX
XX-------------All other memory blocks unused.

SYMBOL TABLE
LABEL
BYTE1
BYTE2
REG0
REG1
REG2
SAVE
START
__18F452
Messages :

Sequential
000000F2 Line numbers
00000032
VALUE

00000000
00000001
00000002
0000002E
00000020
00000001
0 reported,

0 suppressed

opcode

Program Memory Bytes Used: 22

Program Memory Bytes Free: 32746
Errors :
0
Warnings :
0 reported,

0 suppressed

Identifies all memory

locations and opcodes
in the source code

Hex Code (*.HEX)

:020000040000FA
:0400000010EF00F00D
:
10002000F20E006E320E016E002401E3000E026
E2D
:020030000300CB
:00000001FF

*.COD is an executable file.

*.O is the object file

Viewing Your Code

PROG
STRUCTURE

PROG MEMORY
CODE

EEPROM
WATCH

File Select Registers

Indirect Addressing allows the user to access a

location in data memory without giving a fixed
address in the instruction.
This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or
written to.
Since the FSRs are themselves located in RAM
as Special Function Registers, they can also be
directly manipulated under program control.
This makes FSRs very useful in implementing
data structures, such as tables and arrays in
data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands

File Select Registers

Accessing these registers actually accesses the
associated FSR register pair, but also performs a
specific action on it stored value. They are:
POSTDEC: accesses the FSR value, then
automatically decrements it by 1 afterwards
POSTINC: accesses the FSR value, then
automatically increments it by 1 afterwards
PREINC: increments the FSR value by 1,
thenuses it in the operation
PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and
uses the new value in the operation.
n