THE ADDER

Neccesary operation for all dtl.system,DSP or control s/m.

Improving performance of dtl.adder would advance the execution of
the binary operations

i.The binary adder definition

ii.The Full Adder:Circuit Design Consideration

1.Static CMOS adder circuit.
Conventional static CMOS Full adder can be realised
using pull up &pull down with NMOS and PMOS
networks using 28 Tx.
Sum generation to reduce no:of Tx .
CARRY=AB+ACi +Bci
SUM=ABCi +CARRY(A+B+Ci )
Reqd transistors to implement is 28

Adv.
It has Full swing o/p
Does not have threshold loss problem
Adder can be manufactured by a basic conventional
CMOS process with slight mobility degradation

Disadv.
H.delay and h.dynamic power
H.propagation delay
Consumes large area
Intrinsic load capacitance of CARRY signal is high

2.Mirror Adder
Having improved performance than conventional static
full adder.
Tot no.of Tx reqd. to implement is 24.
PMOS n/w and NMOS n/w is identical rather than being a
conduction complement,so the topology is called Mirror
Adder.
Reduces no.of series Tx .bcz adition function is
symmetric

 This does not obey duality principles.

In this carry inversion o/p signal is not reqd.
When A=1,B=0 the CARRY is connected to VDD and
SUM is connected to GND.
When both A & B are high, CARRY with GND & SUM with
VDD.
SUM & CARRY obeys self-duality.

Adv
Full swing o/p without any threshold drop
Easier to design and optimize layouts.
Reduces power consumption
Transistor dimensions are easier to determine.

disadv
Increase the transistor count
Correct aspect ratio should be taken
Great delay to compute PMOS n NMOS.

3.Transmission gate based full

adder
TG full adder designed by using MUX and XORs.
i/p circuits provides both XOR and XNOR o/p.produces
SUM n CARRY.
Delays of SUM n CARRY are same due to use of upper n
lower MUX.
When A=1,B=0 or A=0,B=1 the o/p of XOR is high
which enables MUX1.

adv
All paths have small resistance
CARRY o/p bit is produced first and then SUM will be
calculated
Total no. of Transistor is 24.

disadv
V.poor driving capability
H.pwr dissipation
Difficult to fabricate.

4.Manchester carry chain Adder

Is a chain of pass-Tx. Used to implement the carry
chain.
From full adder truth table three intermediate eqns are
derived:

Finally the next state carry output is given as

Manchester Carry Gates

Pi

VDD

Pi

Co

Ci

Gi
Co

Ci

VDD

Gi

Di
Pi

Static

Dynamic

Manchester Carry Chain

VDD

P0

P1

P2

P3
C3

Ci,0

G1

G0

G3

G2

C0

21

C1

C2

C3

Advantages
It provides faster carry propagation/generation output.
When it is implemented using pass transistor, reduces the total of
transistor count, parasitic capacitances and wiring capacitances.
When it is implemented using dynamic logic offers better speed
performance when compared to static, mirror or TG.

Disadvantages
When it is constructed using static pass transistor logic - threshold
variation problems occurs.
When it is constructed using dynamic logic - charge sharing and
capacitive loading problems are predominant.
Capacitive load together with R of the transistors propagation delay
to increase much more quickly than normal adders.
The propagation delay is quadratic with the no of bits N.

I. Architecture of Ripple carry Adder

The Binary Adder :Logic Design Consideration.
The adder design are classified as low,moderate & high speed adders based on
how carry signals are generated and propagated in the circuit.
First category: Ripple Carry Adder-speed is limited by rippling effects
but
area is limited.
Second category:moderate delay n area- Carry Save Adder(CSA),Carry Look
Ahead Adder(CLaA),Carry increment Adder(CIA), Carry Skip Adder(CSA),
Carry Bypass Adder(CBA) and Carry Select Adder(CSelA).
Last category:H.speed adder or logarithmic or parallel fix adders like
Kogge-stone,Brent kung,Sklansky,Han Carlson,Knowles and

Landner Fischer.

 Ripple Carry Adder

Simplest but slowest adder.
O(n) area and O(n) delay ,n-operand size in bits.
The worst case delay,
t=(n-1)tc +ts
tc =delay thro the carry stage of a FA
ts =delay to compute the sum of the last stage.

Advantages
V.simple ckt realization.
Consumes less pwr.
Compact layout giving the smaller chip area.

Disadv.
The carry bit have to propagate from LSB to MSB.Worst
case delay for N-bit adder is 2N-bit delay.
The performance of the RCA is limited when n-grows
bigger.

 The Carry Byepass Adder(CByA)

 The optimal no:of bits per bypass adder depends on :

The extra delay of the bypass selecting MUX.
The buffering requirements in the carry chain.
The ratio of delay thro the ripple and the bypass paths

Adv.
Smaller propagation delay
Allows carry to skip over groups of m-bits.

Disadv.
Suitable for large size adders.
Area overhead
For N-bit bypass adder the delay is linear and less.

 The Carry Skip Adder

It consists of a simple carry adder with a speed up carry
chain called skip chain.
Fast adder compared to RCA.
It has O() delay .
The chain defines the distribution of ripple carry
blocks,which compose of the skip adder.
It consists of 2 gates.the AND gate accepts the carry-in
bit and compares it to the group propagate signal.
P[I,i+3] =Pi+3 .Pi+2 .Pi+1 .Pi

 Using individual propagate values, the o/p of AND gate

is Ored with Cout of RCA to produce stage o/p.
CARRY= C[i+3] +P[i.,i+3] Ci
If P[I,i+3] =0 ,then the carry out of the group is
determined by C[i+3].
P[I,i+3] =1, then the carry-in bit is Ci =1, then the group
carry-in is automatically sent to the next group of
adders.

Delay calculation

 Carry Select Adder

CSA is divided into 2-sectors,each of them performs 2
additions in parallel,1-assuming a carry-in of zero, the
other a carry-in of 1.
A 4-bit carry select adder generally consists of 2RSAand a MUX.
A CSA speeds 40% to 90% faster than the RCA by
performing additions in parallel and reducing maximum
carry path.

Delay calculation

Adv
Smaller propagation delay when compared with RCA.
Reduces the computation time by pre-computing the sum for all
possible carry bit values.

Disadv.
H.power consumption.
CSA are in the class of fast adders, but they suffer from
fan-out limitation.

 Conditional-sum adder.

 Carry Save Adder

 Parallel prefix adder (PPA) or logarithmic

adder
H.speed adder
The propagation delay is independent of the no.of bits.
This can be categorized into 2-types:
Full-tree parallel-prefix n/w
Sparse-tree parallel prefix n/w

Prefix computation

 Sklansky adder.

 Kogge stone

 Brent kung adder

 Speed/area trade-off in adder design