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  • Comparator Circuit

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    Tsamarul Hizbi
    226 vizualizări17 pagini
    This document discusses combinational logic design practices in Chapter 6, focusing on XOR and XNOR gates, parity circuits, and comparators. It provides truth tables and diagrams showing how XOR and XNOR gates work. Parity circuits use XOR gates in daisy chain or tree structures to check if the number of 1 inputs is odd or even. Comparators are used to compare two binary words and indicate if they are equal, greater than, or less than. MSI chips like the 74x85 implement 4-bit comparators with cascading inputs.

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    Comparator Circuit.ppt

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    This document discusses combinational logic design practices in Chapter 6, focusing on XOR and XNOR gates, parity circuits, and comparators. It provides truth tables and diagrams showing how XOR and XNOR gates work. Parity circuits use XOR gates in daisy chain or tree structures to check if the number of 1 inputs is odd or even. Comparators are used to compare two binary words and indicate if they are equal, greater than, or less than. MSI chips like the 74x85 implement 4-bit comparators with cascading inputs.

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    © All Rights Reserved
    Descărcați ca PPT, PDF, TXT sau citiți online pe Scribd
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    226 vizualizări17 pagini

    Comparator Circuit

    Încărcat de

    Tsamarul Hizbi
    This document discusses combinational logic design practices in Chapter 6, focusing on XOR and XNOR gates, parity circuits, and comparators. It provides truth tables and diagrams showing how XOR and XNOR gates work. Parity circuits use XOR gates in daisy chain or tree structures to check if the number of 1 inputs is odd or even. Comparators are used to compare two binary words and indicate if they are equal, greater than, or less than. MSI chips like the 74x85 implement 4-bit comparators with cascading inputs.

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    din 17

    ECE 3110: Introduction to Digital Systems

    Chapter 6
    Combinational Logic Design
    Practices

    XOR, Parity
    Circuits,
    Comparators

    Exclusive OR and Exclusive NOR Gates

    XOR

    XNOR :

    X Y X 'Y X Y '

    ( X Y )' X Y X 'Y '

    Truth Table :
    X
    0
    0
    1
    1

    Y
    0
    1
    0
    1

    XOR XNOR
    0
    1
    1
    0
    1
    0
    0
    1

    XOR

    X
    F

    XOR
    2

    XOR and XNOR Symbols


    Equivalent Symbols of XOR gate

    Equivalent Symbols of XNOR gate

    Any 2 signals (inputs or outputs) may be


    complemented without changing the resulting
    logic function

    SSI XOR and XNOR


    74x86 :
    4 XOR gates
    74x266:
    4 XNOR gates with open collector or open
    drain output

    XOR Application: Parity


    Circuit
    Odd Parity Circuit : The output is 1 if odd number of inputs are 1
    Even Parity Circuit : The output is 1 if even number of inputs are
    1
    Example :
    4-bit Parity Circuit
    I0
    I1

    EVEN

    I2

    ODD

    I3

    Daisy-Chain Structure
    Input : 1101

    I0

    EVEN

    I1

    ODD

    I2
    I3

    Tree structure

    Odd Parity output : 1


    Even Parity output : 0
    5

    MSI Parity Circuit :


    74x280

    Parity-Checking Application: memory

    Comparators
    Compares Two binary words and indicate if
    they are equal
    A

    Comparator

    A=B?

    Magnitude Comparators :
    A
    B

    Comparator

    A=B
    A>B
    A<B

    Equality Comparators
    1-bit comparator

    4-bit
    comparator

    EQ_L9

    Iterative Comparator

    10

    Multi-bit Iterative
    Comparator

    11

    Meon kance Begang

    12

    MSI Comparator : 74x85

    4 bit comparator
    3 outputs : A=B, A<B, A>B
    3 Cascading inputs
    Functional Output equations :
    (A>B OUT)= (A>B)+(A=B).(A>B IN)
    (A<B OUT)= (A<B)+(A=B).(A<B IN)
    (A=B OUT)= (A=B).(A=B IN)
    Cascading inputs initial values :
    (A=B IN) =1
    (A>B IN) =0
    (A<B IN) =0

    74x85
    A<BIN A<BOUT
    A=BIN A=B OUT
    A>BIN A>BOUT
    A0
    B0
    A1
    B1
    A2
    B2
    A3
    B3

    13

    8 bit Comparator
    +5V
    74x85

    74x85

    A<BIN A<BOUT

    A<BIN A<BOUT

    A<B

    A=BIN A=B OUT

    A=BIN A=B OUT

    A=B

    A>BIN A>BOUT

    A>BIN A>BOUT

    A>B

    A0

    A0

    A4

    A0

    B0

    B0

    B4

    B0

    A1

    A1

    A5

    A1

    B1

    B1

    B5

    B1

    A2

    A2

    A6

    A2

    B2

    B2

    B6

    B2

    A3

    A3

    A7

    A3

    B3

    B3

    B7

    B3

    Least Significant bits

    Most Significant bits

    14

    8-bit Magnitude
    Comparator

    15

    Other
    conditions

    16

    Next
    Adders, subtractors, ALUs

    Reading Wakerly CH-6.10-6.11

    17

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