8051 Core Specific

ation

Outlines
Introduction
Architecture
Operation
Registers

Introduction

MCS-51 family, originally designed by

Intel in the 1980s
Used in a large percentage of embedde
d systems
Includes several on-chip peripherals,
like timers and counters
128 bytes of on-chip data memory and
up to 4K bytes of on-chip program mem
ory

Features (1/2)

8-bit CPU optimized for control applications

Extensive Boolean processing (single-bit logic) ca
pabilities
64K Program Memory address space
64K Data Memory address space
Up to 4K bytes of on-chip Program Memory
128 bytes of on-chip Data RAM
32 bi-directional and individually addressable I/O
lines
Two 16-bit timer/counters
6-source/5-vector interrupt structure with two pri
ority levels

Features (2/2)

Outlines

Introduction
Architecture
Operation
Registers

Architecture

Memory Organization
CPU Clock
Interrupt Structure
Port Structures
Timer/Counters
Reset

Memory Organization (1/3)

Logical separation of program and data memo

ry

Separate address spaces for Program (ROM) and D

ata (RAM) Memory
Allow Data Memory to be accessed by 8-bit addre
sses quickly and manipulated by 8-bit CPU

Program Memory

Only be read, not written to

The address space is 16-bit, so maximum of 64K
bytes
Up to 4K bytes can be on-chip (internal) of 805
1 core
PSEN (Program Store Enable) is used for access
to external Program Memory

Memory Organization (2/3)

Data Memory
Includes 128 bytes of on-chip Data Memory
which are more easily accessible directly
by its instructions
There is also a number of Special Functio
n Registers (SFRs)
Internal Data Memory contains four banks
of eight registers and a special 32-byte
long segment which is bit addressable by
8051 bit-instructions
External memory of maximum 64K bytes is a
ccessible by movx

Memory Organization (3/3)

Internal Data Memory, 128 bytes

CPU Clock

8051 microcontroller has a clock inpu

t pin

Interrupt Structure

The 8051 provides 4 interrupt sources

Two external interrupts
Two timer interrupts

Additional description follows in Ope

rations chapter

Port Structures (1/3)

The 8051 contains four I/O ports

All four ports are bidirectional
Each port has SFR (Special Function R
egisters P0 through P3) which works l
ike a latch, an output driver and an
input buffer
Both output driver and input buffer o
f Port 0 and output driver of Port 2
are used for accessing external memor
y

Port Structures (2/3)

Accessing external memory works like

this
Port 0 outputs the low byte of external m
emory address (which is time-multiplexed
with the byte being written or read)
Port 2 outputs the high byte (only needed
when the address is 16 bits wide)

Port Structures (3/3)

Port 3 pins are multifunctional

The alternate functions are activated
with the 1 written in the correspondi
ng bit in the port SFR

Read-Modify-Write Feature
(1/2)

When reading a port some instructions

read the latch and others read the pi
n
The instructions that read the latch
rather than the pin are the ones that
read a value (possibly change it), an
then rewrite it to the latch are call
ed read-modify-write instructions

Read-Modify-Write Feature
(2/2)

Timer/Counters

The 8051 has two 16-bit Timer/Counter

registers
Timer 0
Timer 1

Both can work either as timers or eve

nt counters
Both have four different operating mo
des from which to select (all modes a
re described in Operations chapter)

Reset

The reset input is the RST pin

Outlines

Introduction
Architecture
Operation
Registers

Instruction Set

Optimized for 8-bit control applicati

ons
Fast addressing modes for accessing i
nternal RAM in order to facilitate by
te operations on small data structure
s
Good for systems that require a lot o
f Boolean processing because of its e
xtensive support for one-bit variable
s as a separate data type

Addressing Modes (1/3)

Direct Addressing

Operand is specified by an 8-bit address field

in the instruction
This address mode is possible only for addressi
ng internal Data RAM and SFRs

Indirect Addressing

The instruction specifies a register which cont

ains the address of the operand
The address register for 8-bit addresses can be
R0 or R1 of the selected bank, or the Stack Poi
nter
The address register for 16-bit addresses can o
nly be 16-bit data pointer register, DPTR
Both internal and external RAM can be indirectl
y addressed

Addressing Modes (2/3)

Register Instructions

Special instructions are used for accessing fou

r register banks (containing R0 to R7)
This instructions have 3-bit register specifica
tion within the opcode
This way of accessing registers is much more ef
ficient because of no need for the address byte
When such instruction is executed one of regist
ers in selected ban is accessed
Register bank is selected by two bank select bi
ts in PSW

Addressing Modes (3/3)

Register-Specific Instructions

Immediate Constants

These are instructions which are specific to a

certain register and they dont need an address
byte (they always operate with the same registe
r)
The value of a constant follows the opcode
MOV A, #10 loads the Accumulator with the dec
imal number 10

Indexed Addressing

Only Program Memory can be accessed and it can

be a read
Used for reading look-up tables in Program Memo
ry and case jump instruction

Instruction Types of 8051

Arithmetic Instructions
Logical Instructions
Data Transfers
Lookup Tables
Boolean Instructions
Jump Instructions

Arithmetic Instructions

Logical Instructions

Data Transfers

Lookup Tables

Boolean Instructions

Jump Instructions

Timer/Counters

8051 has two 16-bit Timer/Counter registers

Timer/Counter 0
Timer/Counter 1

These registers can be used as timers or as

event counters
When a register is in Timer state, it is
incremented every machine cycle
In Counter state, the register is increme
nted when there is a 1-to-0 transition at i
ts external input pin, pin T0 or T1
Both registers have additional four operati
ng modes

Timer/Counter Modes

The selection for Timer or Counter is do

ne by control bits C/T in the TMOD register
Both Timer/Counters have four operating mod
es, which Modes 0, 1 and 2 are the same for
both Timer/Counters, Mode 3 is different
Modes are selected by bit pairs (M1, M0) in
TMOD SFR
Another SFR used for work with Timer/Counte
rs is TCON containing flag (TFx) and contro
l (TRx) bits

Mode 0

Both Timer 1 and Timer 0 in Mode 0 operate as an

8-bit Counters (with a divide-by-32 prescaler)
Timer register is configured as a 13-bit register
consisting of all 8 bits of TH1 and the lower 5 bi
ts of TL1
The upper 3 bits of TL1 are indeterminate and shou
ld be ignored
Setting the run flag (TR1) does not clear the regi
ster
Timer interrupt flag TF1 is set when the count rol
ls over from all 1s to all 0s
Mode 0 operation is the same for Timer 0 as for Ti
mer 1. Just substitute Timer 0 for the correspondi
ng Timer 1 signals

Mode 1

Mode 1 is the same as Mode (for both

Timers), except that the Timer regist
er is configured as 16-bit register

Mode 2

Both Timer registers are configured a

s an 8-bit Counters (TL1 and TL0) wit
h automatic reload
Overflow from TL1 (TL0) sets TF1 (TF
0) and also reloads TL1 (TL0) with th
e contents of Th1 (TH0), which is pre
set by software
The reload leaves TH1 (TH0) unchanged

Mode 3

Mode 3 is different for Timer 1 and Timer 0

Timer 1 just holds its count. It operates the same
as when TR1 is set to 0
For Timer 0 is different, TL0 and TH0 of Timer 0 a
re established as two separate counters
TL0 uses Timer 0 control bits for its work: C/T, G
ATE, TR0, ~INT0, and TF0
TH0 is locked into a timer function (counting mach
ine cycles) and takes over the use of TR1 and TF1
from Timer 1. TH0 is now actually in control of T
imer 1 interrupt
Mode 3 is provided for applications that require a
n extra 8-bit timer or counter

With Timer 0, 8051 looks like it has three Timer/Counters

When Timer 0 in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or can st
ill be used in any application not requiring an interrupt

Interrupt (1/3)

8051 provides 4 interrupt sources

2 external interrupts
2 timer interrupts

They are controlled via two SFRs, IE

and IP
Each interrupt source can be individu
ally enabled or disabled by setting o
r clearing a bit in IE (Interrupt Ena
ble). IE also exists a global disable
bit, which can be cleared to disable
all interrupts at once

Interrupt (2/3)

Each interrupt source can also be individua

lly set to one of two priority levels by se
tting or clearing a bit in IP (Interrupt Pr
iority)
A low-priority interrupt can be interrupted
by high-priority interrupt, but not by anot
her low-priority one
A high-priority interrupt cant be interrup
ted by any other interrupt source
If interrupt requests of the same priority
level are received simultaneously, an inter
nal polling sequence determines which reque
st is serviced, so within each priority lev
er there is a second priority structure

Interrupt (3/3)

This internal priority structure is d

etermined by the polling sequence, sh
own in the following table

External Interrupts

External interrupts ~INT0 and ~INT1 have two ways

of activation

Level-activated
Transition-activated

This depends on bits IT0 and IT1 in TCON

The flags that actually generate these interrupts
are bits IE0 and IE1 in TCON
On-chip hardware clears that flag that generated a
n external interrupt when the service routine is v
ectored to, but only if the interrupt was transiti
on-activated
When the interrupt is level-activated, then the ex
ternal requesting source is controlling the reques
t flag, not the on-chip hardware

Timer 0 and Timer 1 Interr

upts

Timer interrupts are generated by TF0

and TF1 flags in their respective Tim
er/Counter registers
Similarly like in the case of transit
ion-activated external interrupts, th
e flag that generated an interrupt is
cleared by the on-chip hardware when
the service routine is vectored to

Handling of Interrupts (1/

5)

When interrupt occurs (or correctly, when t

he flag for an enabled interrupt is found t
o be set (1)), the interrupt system generat
es an LCALL to the appropriate location in
Program Memory, unless some other condition
s block the interrupt
Several conditions can block an interrupt

An interrupt of equal or higher priority level

is already in progress
The current (polling) cycle is not the final cy
cle in the execution of the instruction in prog
ress
The instruction in progress is RETI or any write
to IE or IP registers

Handling of Interrupts (2/

5)

If an interrupt flag is active but not bein

g responded to for one of the above conditi
ons, must be still active when the blocking
condition is removed, or the denied interru
pt will not be serviced
Next step is saving the registers on stack.
The hardware-generated LCALL causes only th
e contents of the Program Counter to be pus
hed onto the stack, and reloads the PC with
the beginning address of the service routin
e
In some cases it also clears the flag that
generated the interrupt, and in other cases
it doesnt. It clears an external interrupt

Handling of Interrupts (3/

5)

Having only PC be automatically saved gives

programmer more freedom to decide how much
time to spend saving other registers. Progr
ammer must also be more careful with proper
selection, which register to save
The service routine for each interrupt begi
ns at a fixed location. The interrupt locat
ions are spaced at 8-byte interval, beginni
ng at 0003H for External Interrupt 0, 000BH
for Timer 0, 0013H for External Interrupt 1
and 001BH for Timer 1, shown in the followi
ng tables

Handling of Interrupts (4/

5)

Handling of Interrupts (5/

5)

Execution of service routine continues from

that location until the end, that is until
it encounters RETI.
RETI instruction does two things

It informs the processor that this interrupt ro

utine is finished
Secondly, reloads the PC from the top bytes fro
m the stack

Similar result could be accomplished with R

ET, with the distinction that the interrupt
control system would be thinking an interru
pt was still in progress

Reset

The reset input is RST pin

To accomplish a reset the RST pin must be held hig
h for at least two machine cycles
In the response on the RST signal, CPU generates a
n internal reset
The external reset signal is asynchronous to the i
nternal clock
In the internal reset algorithm, 0s are written to
all the SFRs except the port latches and Stack Poi
nter
The port latches are initialized to FFH and Stack
Pointer to 07H
Driving ALE and PSEN pins to 0 while reset is acti
ve could cause the device to go into an indetermin
ate state
The internal RAM is not affected by reset. On powe

Outlines

Introduction
Architecture
Operation
Registers

8051 Registers

PSW: Program Status Word

(bit addressable)

The PSW register contains several sta

tus bits that reflect the current sta
te of the CPU

IE: Interrupt Enable Register

(bit addressable)

If the bit is 0, the corresponding in

terrupt is disabled. Otherwise, the i
nterrupt is enabled.

IP: Interrupt Priority Regist

er
(bit addressable)

If the bit is 0, the corresponding in

terrupt has a lower priority and if t
he bit is 1, the interrupt has a high
er priority

TCON: Timer/Counter Control R

egister (bit addressable)

TMOD: Timer/Counter Mode Cont

rol Register (not bit address
able)