CHAPTER-II

ARCHITECTURE
OF 8051

Pin diagram of 8051

Pins of 8051

contd

A / D Address or data.
A Address.
EA External access or external enable.
Vpp EPROM voltage
Vcc +5v supply.
RST Reset pin
PSEN Program enable
RxD Receive data
TxD Transmit data
INTo Interrupt zero
INT1 Interrupt one

Pins of 8051

To Timer zero
T1 Timer one
XTAL1 Crystal input one
XTAL2 Crystal input two
Po Port zero
P1 Port one
P2 Port two
P3 Port three
WR Write enable
RD Read enable
ALE-address latch enable

contd

Pins of MCS 8051

XTAL1 & XTAL2

Input on pin 9
Used for resetting microcontroler. Logical high signal
on these pin resets the microcontroller (clears all the
registers)

PSEN bar

Used for connecting Quartz crystal oscillator.

Reset

contd

The program store enable is an output signal on pin 29

This signal is used for fetching instructions from
external code memory.

EA bar

The external access, on pin 31

Used for enabling or disabling the on-chip ROM.
When set, the 8051 executes instructions in internal
ROM
If not set the 8051 will always execute instructions in

PORTS OF MCS 8051

Port 0

Port 1

pins 1 to 8 make up the 8-bit I/O port 1.

Port 2

pins 32 to 39 make up the 8-bit I/O port 0. However, if

external memory is used, these lines are used as a
multiplexed address and data bus.

pins 21 to 28 make up the 8-bit I/O port 2. However, if

external memory is used, these lines make up the highbyte of the external address (A8 to A15).

Port 3

pins 10 to 17 make up the 8-bit I/O port 3. However,

each of these eight pins also has an alternate function,
as detailed in the table below.

Architecture of 8051
microcontroller

Building Blocks of 8051

CPU
Internal Memory
Data memory
Program memory

I/O ports
Timer & Counter
Serial Data Communication ports

CPU
-

CPU consists of ALU and Registers

ALU: Arithmetic and Logical Unit
-

Performs Arithmetic and Logical operations

Arithmetic Unit performs operations like
addition , subtraction , multiplication &
division.
Logical unit can perform logical functions like
AND ,OR , NOT ,EXOR , EXNOR, rotate &
complement operations.

Registers

Provides small amount of storage on CPU

A, B, PSW, SP, COUNTER, DATA POINTER

Accumulator and B
Registers

ACCUMULATOR
One of the Special Function Register (SFR)
8 bit general purpose register
Used for storing one of the operand and results in
large number of instructions.
Used also in transferring data from one register to
other register
B Register
An SFR,
Used with Accumulator for multiplication & division
operations
Stores upper 8 bit of the product & remainder of
division
Stores carry in addition and barrow in subtraction
operations.

Program status work

(PSW)

A bit addressable register that holds all the flags.

Flags are single bit registers .

Flags are provided for testing the outcome of an

instruction's execution

Flags of PSW register of 8051 are as shown

below
MSB
LSB

CY AC F
0

RS1 RS0 O
V

Flags of PSW

Carry Flag (CY, PSW7):

Used as Carry/Barrow bit

Set when carry or barrow is generated

Auxiliary Carry Flag (AC, PSW6)

+
1

Used for operations with BCD(Binary Coded

Decimal)
If carry/Barrow is generated from third to
fourth bit as show below, AC flag is set
D7
1
1
1

D6
0
0
1

D5
0
0
0

D4
1
1
1

D3 D2 D1 Do
1
0 0 0
1
0 0 0
0
1 1 0

Flags of PSW

F0 (Flag Zero, PSW5)

contd

Flag zero is user defined general purpose flag

RS1 & RS0 flags ( PSW2 & PSW3)

Called as register bank select flags

Selection of register banks depends on RS1&
RS0 flags. Selection is done as shown .
RS1
0
0
1
1

RS0
0
1
0
1

Register bank
0
1
2
3

Flags of PSW

Overflow flag (OV, PSW2)

contd

Set after an addition or subtraction operation

if the result in the accumulator is outside 8-bit
range.

PSW1: Not used

Parity Flag (P, PSW0):

Parity flag is set if the result of operation

contains odd number of ones .
If result contains even number of ones & then
these flag contains zero

Data Pointer Register

(DPTR) Program Counter
(PC)

DPTR

16 bit register used for addressing external

memory
Made up of two 8 bit registers

Data Pointer High

Data Pointer Low

This is also commonly used for temporary

storage and runtime results not related to
memory locations

PC

A 16 bit register which points to the next

instruction to be executed
Incremented automatically after every
instruction is fetched

General Purpose
Registers

32 general purpose registers

Arranged in 4 banks
Each bank contains eight registers
Banks can be selected by using RS0
and RS1 flags of PSW
RS1
0
0
1
1

RS0
0
1
0
1

Register bank
0
1
2
3

Address
00 - 07H
08 - 0FH
10 - 17H
18 - 1FH

Stack Pointer

8 bit register at location 81 H

Contains address of data currently on the top of
the stack
Stack is used for temporarily storing the data
Operates on basis of Last In Fist Out
Putting data on to stack is called as pushing on
to stack
Taking data from stack is called as popping the
stack
On power-on or reset SP is set to 07H
When pushing data SP is incremented by 1
When popping off SP is decremented by 1

Stack pointer

Stack is a section of RAM used by the CPU to

store information temporally , the CPU need
these storage since there are only a limited
number of registers , if stack is section of RAM
then there must be register inside the CPU to
point to it. The register used to access the stack
is called the stack pointer register(SP). The stack
pointer is a 8 bit register which means it can
take values from 00 to FFH. If the register SP
contains values 07 then 08 is the present location
being used for the stack. The storing of the
contents of CPU register in the stack is called the
push & loading the contain of the stack back into
the CPU register is called a pop.

Pushing & Popping

Pushing onto a stack:In the 8051 microcontroller the

stack pointer is pointing to the last used location
of the stack as we push data onto the stack, the
stack pointer is incremented by one. In example
one we see that
the register are saved on the stack & SP is
incremented by one, we can notice that for every
byte of data saved on stack, the SP is
incremented only once.
POPing from the stack:POPing the contains of the stack
back into the given register is the opposite
process of pushing , with every POP the top byte
of the stack is copied on to the register specified
by the instruction & the stack pointer is

Stack in the 8051

7FH
Scratch pad
30H
2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H

Register Bank 3
Register Bank 2
Register Bank 1( Stack)
Register Bank 0

Example:
MOV
MOV
MOV
PUSH
PUSH
PUSH

PUSH OPERATION

R6,#25H
R1,#12H
R4,#F3H
R6
R1
R4

0BH

0BH

0BH

0BH

0AH

0AH

0AH

0AH

F3

09H

09H

09H

12

09H

12

08H

08H

08H

25

08H

25

Start SP=07H

25

SP=08H

SP=09H

SP=0AH

Example:
MOV
MOV
MOV
PUSH
PUSH
PUSH
POP
POP
POP
0BH

R6,#25H
R1,#12H
R4,#F3H
R6
R1
R4
R4
R3
R1
0BH

0BH

0BH

0AH

0AH

09H

09H

0AH

F3

0AH

09H

12

09H

08H

25

08H

Start SP=0AH

POP OPERATION

12
25

SP=09H

08H

25

SP=08H

08H
SP=07H

Stack Pointer Example

MOV R6 , #25H
MOV R1 , #12H
MOV R4 , # 0FH
Push R6
Push R1
Push R4
Pop R6
Pop R1
Pop R4

Internal Memory

Internal Memory
Data Memory 128 byte on-chip RAM
Program Memory 4K byte on-chip ROM

8051 uses two different types of memory

Program memory which is used for holding the

program.
Data memory is used for temporarily storage of data

Program Memory

Data Memory
FFH

SFR Space (128 bytes)

80H
7FH

Internal Data Memory

(128 bytes)
00H

External data
memory of size
64kBytes can be
used.

8051- RAM
MSB
7FH
2FH
2EH
2DH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
23H
22H
21H
20H
17H
10H
08H
00H

LSB
Scratch Pad Area

7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07

7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06

7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05

7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
Register Bank 3
Register Bank 2
Register Bank 1
Register Bank 0

7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04

7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02

79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01

78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00

DESCRIPTION OF
INTERNAL RAM

The 8051 has 128 bytes of internal data memory which are
assigned address from 00 to 7FH . These memory area are
divided into 3 different groups.
Total of 32 bytes from location 00 to 1FH set aside for register
banks. They are arranged as 4 register banks Bo to B3 ,
consisting of 8 registers Ro to R7.
The total of 16 bytes from location 20H to 2FH are set aside for
bit addressable area , in general in microprocessor data
transmission is one byte at a time, so if we want to change one bit
we have to Access the hole byte , but in 8051 we can access one
bit instead of one byte. These ability access data in a single bit
instead of hole byte makes 8051 one of the more powerful 8 bit
microcontroller . Instruction that are used for bit addressable
operation are;
SETB bit.
CLR bit.
3.From 30H to 7FH is kept aside for storing some data & we
can call these as scratch pad RAM.

TIMER

The 8051 has 2 Timers.

Timer 0 & Timer 1
They can be used either timers or
counters
Both timer 0 & timer 1 are 16 bit
registers.

Timer 0 Register

The 16 bit register timer 0 is accessed as lower

byte & higher byte .

The lower byte register is called as TLO

Higher byte register is called THO.

These registers can be accessed like any other

register such as register A , register B , Ro etc.

TH0
D1
5

D14

D1
3

D1
2

D11

TL0
D1
0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Timer 1 Register

The 16 bit register timer 1 is accessed as lower

byte & higher byte .

The lower byte register is called as TL1

Higher byte register is called TH1.

These registers can be accessed like any other

register such as register A , register B , Ro etc.

TH1
D1
5

D14

D1
3

D1
2

D11

TL1
D1
0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

TMOD Register

Both timer 0 & 1 use the same register

called TMOD to set the various timer
operation modes .
TMOD is a 8 bit register in which the
lower 4 bits are set aside for timer 0 &
upper 4 bits are set aside for timer 1 .
In each case the lower 2 bits are used to
setGATE
the timer
mode & upper 2 bits are
C/T M1 M GAT C/T M1 M0
used to specify the
0 operation.
E

TMOD Register

C/T
This bit represent whether the timer or counter
is used .
If C/T=0 then it is a timer operation ,
If C/T=1 then it is a counter operation.

M1

Mo
Gate

M1 is mode bit 1.
Mo is mode bit zero.

Every timer has a means of starting & stopping, some

timers do this by software & some by hardware .
If gate=0 then timer uses software to start & stop .
If gate=1 then timer uses hardware to start & stop.

TCON register ( Timer control

register)

A 8 bit register
The upper 4 bit is set aside to store timer 0 & timer 1 .
TF means timer over flow .
TR means timer start .
TCON is a bit addressable register
If TR0=1 , it means that timer zero is to be started .
If TF 0=1,it means over flow has occurred in timer 0,else
no overflow
The lower 4 bits are set aside for controlling & interrupt
bits .
TF1

TR1

TF0

TR0 CO TROL LING &

NIN RRUP T
BIT
TE
S

Serial data
communication

Uses register SBUF to hold the data

to be transmitted or received.

SCON controls the data

communication
PCON is used to set the baud rate .
Pins RxD & TxD connects 8051
serial data communication.

Addresses of SFR