CHAPTER 3: THYRISTORS

Prepared By: SANDEEP KUMAR K

ASSISTANT PROFESSOR
DEPARTMENT OF MECHATRONICS
ACHARYA INSTITUTE OF TECHNOLOGY

Introduction
Thyristor is the most important type of

power semiconductor devices.

They are extensively used in power
electronic circuits.
They are operated as bi-stable switches
from non-conducting to conducting state.
A Thyristor is a four layer, semiconductor of
p-n-p-n structure with three p-n junctions. It
has three terminals, the anode, cathode
and the gate.
The word Thyristor is coined from Thyratron
and transistor. It was invented in the year

SILICON CONTROLLED RECTIFIER

(SCR)
C a th o d e

G a te

n
J3

10

19

cm

-3

n
-

10

17

cm

-3

J2
n
J1

p
p

10
10
10

13

17
19

-5 x 1 0
cm
cm

14

cm

-3

10

19

cm

-3

-3
-3

Anode

1 0 m
3 0 -1 00 m
5 0 -1 0 0 0 m
3 0 -5 0 m

QUALITATIVE ANALYSIS

When the anode is made positive with

respect the cathode junctions j1 and j3 are

forward biased and junction j2 is reverse
biased.
With anode to cathode voltage being
small, only leakage current flows through
the device. The SCR is then said to be in
the forward blocking state.
If VAK is further increased to a large value,
the reverse biased junction will breakdown
due to avalanche effect resulting in a large
current through the device.
The voltage at which this phenomenon
occurs is called the forward breakdown
voltage (VBO)

V-I Characteristics of SCR

Effects on gate current on

forward blocking voltage

LATCHING CURRENT (IL)

After the SCR has switched on, there is a
minimum current required to sustain conduction
even if the gate supply is removed. This current is
called the latching current. associated with turn
on and is usually greater than holding current.
HOLDING CURRENT (IH)
After an SCR has been switched to the on state a
certain minimum value of anode current is
required to maintain the Thyristor in ON state. If
the anode current is reduced below the critical
holding current value, the Thyristor cannot
maintain the current through it and turns OFF.

QUANTITATIVE ANALYSIS
TWO TRANSISTOR MODEL

Derivation for anode current

General transistor equation is
IC= IE + ICBO
For transistor 1

IC1= 1IE1+ ICBO1 ; IE1 = IA

There fore

IC1= 1IA+ ICBO1 ---------

Eq 1

For transistor 2

IC2= 2IE2+ ICBO2 ; IE2 = IK and IK = IA + IG

There fore
IA= IC1 + IC2

IC2= 2(IA + IG )+ ICBO2 ------ Eq 2

IA=1IA+ ICBO + 2(IA + IG )+ ICBO

1

I C2 I B1

2 I g I CBO1 I CBO 2
IA
1 1 2

THYRISTOR TURN ON

Thyristor is turned ON by increasing

the Anode current,
this can be accomplished by one of the
following ways
Thermal Turn on or High Temperature
Triggering
Light Triggering
High Voltage Triggering
dv/dt Triggering
Gate Triggering

Thermal Turn on or High

Temperature
The width of depletion layer of SCR

decreases with increase in junction

temperature.
Therefore in SCR when VARis very near its
breakdown voltage, the device is triggered
by increasing the junction temperature.
By increasing the junction temperature the
reverse biased junction collapses thus the
device starts to conduct.
This type of turn on many cause thermal
run away and is usually avoided.

Light Triggering
For light triggered SCRs a special terminal

is made inside the inner P layer instead of

gate terminal.
When light is allowed to strike this terminal,
free charge carriers are generated.
When intensity of light becomes more than
a normal value, the Thyristor starts
conducting.
This type ofSCRsare called asLASCR

High Voltage Triggering

In this mode, an additional forward voltage is applied

between anode and cathode.

When the anode terminal is positive with respect to
cathode(VAK) , Junction J1 and J3 is forward biased and
junction J2 is reverse biased.
No current flows due to depletion region in J2 is
reverse biased (except leakage current).
As VAKis further increased, at a voltage V BO(Forward
Break Over Voltage) the junction J2 undergoes
avalanche breakdown and so a current flows and the
device tends to turn ON(even when gate is open)
This type of turn on is destructive and should be
avoided.

dv/dt Triggering
When the device is forward biased, J1 and J3

are forward biased, J2 is reverse biased.

Junction J2 behaves as a capacitor, due to the
charges existing across the junction.

If voltage across the device is V, the charge by Q and

capacitance by C then,
ic= dQ/dt
Q = CV
ic= d(CV) / dt
= C. dV/dt + V. dC/dt
as dC/dt = 0
ic= C.dV/dt
Therefore when the rate of change of voltage across
the device becomes large, the device may turn ON,
even if the voltage across the device is small.
A high value of charging current may damage the
Thyristor and the device must be protected against
high .
The manufacturers will specify the allowable .

Gate Triggering
This is most widely used SCR triggering

method.
Applying a positive voltage between gate
and cathode can Turn ON a forward biased
Thyristor.
When a positive voltage is applied at the
gate terminal, charge carriers are injected
in the inner P-layer, thereby reducing the
depletion layer thickness.
As the applied voltage increases, the
carrier injection increases, therefore the
voltage at which forward break-over occurs
decreases

Three types of signals

are used for gate
triggering.
1. DC gate triggering
2. AC Gate Triggering
3. Pulse Gate Triggering

DC gate triggering
A DC voltage of proper polarity is applied

between gate and cathode ( Gate terminal is

positive with respect to Cathode).
When applied voltage is sufficient to produce the
required gate Current, the device starts
conducting.
One drawback of this scheme is that both power
and control circuits are DC and there is no
isolation between the two.
Another disadvantages is that a continuous DC
signal has to be applied. So gate power loss is
high.

AC Gate Triggering:Here AC source is used for gate signals.

This scheme provides proper isolation

between power and control circuit.

Drawback of this scheme is that a
separate transformer is required to step
down ac supply.
There are two methods of AC voltage
triggering namely (i) R Triggering (ii) RC
triggering

3. Pulse Gate Triggering

In this method the gate drive

consists of a single pulse appearing

periodically (or) a sequence of high
frequency pulses.
This is known as carrier frequency
gating.
A pulse transformer is used for
isolation.
The main advantage is that there
is no need of applying continuous

SWITCHING CHARACTERISTICS (DYNAMIC

CHARACTERISTICS)
THYRISTOR TURN-ON CHARACTERISTICS

di/dt protection
A Thyristor requires minimum time to

spread the current conduction

uniformly through out the junctions.
If the rate of rise of Anode current is
very fast compared to the spreading
velocity of turn on process,
HOTSPOT heating will occur and
device may fail due to excessive
temperature.
The Thyristor can be protected from

di/dt protection

di VS

dt LS

dv/dt protection
The dv/dt across the Thyristor is limited by

using snubber circuit as shown in figure (a)

below. If switch is closed at t=0 , the rate
of rise of voltage across the Thyristor is
limited by the capacitor . When Thyristor is
turned on, the discharge current of the
capacitor is limited by the resistor as
shown in figure (b) below.

Fig. (a)
Fig. (b)

The voltage across the Thyristor will rise

exponentially as shown in fig above.

1
VS i t RS i t dt Vc 0 for t 0
C

Assuming Vc(0)=0

Now applying Laplace

transform

OR

Now applying Inverse Laplace transform we get

Where

s RS CS

GATE TRIGGERING METHODS

The different methods of gate triggering are
the following

R-triggering.
RC triggering.
UJT triggering.

RESISTANCE TRIGGERING
vO

LO AD

v S = V m s in t

A simple resistance triggering circuit is as

shown.
The resistor R1 limits the current through

the gate of the SCR. R2 is the variable

resistance added to the circuit to achieve
control over the triggering angle of SCR.
Resistor R is a stabilizing resistor. The

diode D is required to ensure that no

negative voltage reaches the gate of the
SCR.

V m s in t
3

Vg

Vo

Vg

Vgt

Vgp

Vgp

Vgt

Vg

Vgp= Vgt

4
t

Vgp>Vgt

t
Vo

io
270

VT

90

(a )

3
t

t
Vo

VT

io

= 90
(b )

io

VT

4
t

t
< 90
(c )

Design
V
With , R2=0 we need to ensure
I that I gm
,
R
V
where
is the
R1 m
I gm
maximum
R2 or
0 peak gate current of the SCR.
Therefore
Also with
V R
Vgm
V,gmwe
mneed to ensure that the
R
voltage drop acrossR1resistor
R does not
maximum
Vgm R1 Vgm R gate
Vm R voltage
exceed , the
m
1

Vgm R1 R Vm Vgm
R

Vgm R1
Vm Vgm

gm

RESISTANCE CAPACITANCE
TRIGGERING
v

LO AD

+
R

v S = V m s in t
V

Capacitor C in the circuit is connected to shift the

phase of the gate voltage.

Diode D1 is used to prevent negative voltage from
reaching the gate cathode of SCR.
In the negative half cycle, the capacitor charges to
the peak negative voltage of the supply (-Vm)
through the diode D2 .
The capacitor maintains this voltage across it, till
the supply voltage crosses zero. As the supply
becomes positive, the capacitor charges through
resistor R from initial voltage of (-Vm) , to a
positive value.
When the capacitor voltage is equal to the gate
trigger voltage of the SCR, the SCR is fired and the
capacitor voltage is clamped to a small positive
value

Waveform
V m s in t
V gt

vs
-/2

-/2

0
0
vc

a
vo

vT

V m s in t
V gt

vs

vc

t
a

vo
t

vc

Vm

vc

Vm
t

vT
Vm

-V m
(a )

-V m
(b )

(2 + )

Case 1: R Large.
When the resistor R is large, the time taken for the
capacitance to charge from (-Vm) to Vgt is large,
resulting in larger firing angle and lower load voltage.
Case 2: R Small
When R is set to a smaller value, the capacitor
charges at a faster rate towards Vgt resulting in early
triggering of SCR and hence VL is more.
When the SCR triggers, the voltage drop across it
falls to 1 1.5V. This in turn lowers, the voltage across
R & C. Low voltage across the SCR during conduction
period keeps the capacitor discharge during the
positive half cycle.

RC FULL WAVE
v

LOAD

D1

D3

R
v

V
-

vS= V

s in t

D2

D4
-

Waveform
vs

vs

V m s in t

V m s in t

t
vd

vd

vo

vd

vc

vc

vgt vc

vT

(a )

vgt

vo

vT

(b )

UNI-JUNCTION TRANSISTOR (UJT)

B

E t a - p o in t
R

B
B2

E t a - p o in t

A
R

n -ty p e

p -ty p e
E

B1

Ie

(a)

(b)

B1

BB

B2

(c)

BB

UJT is an n-type silicon bar in which p-type

emitter is embedded. It has three terminals

base1, base2 and emitter E.
Between B1 and B2 UJT behaves like
ordinary resistor and the internal
resistances are given as RB1 and RB2 with
emitter open RBB=RB1+RB2 .
When VBB is applied across B1 and B2 , we
find that potential
at A is

V R
R
VAB1

BB

B1

RB1 RB 2

B1
VBB

B1
B 2

 is intrinsic stand off ratio of UJT and ranges

between 0.51 and 0.82. Resistor RB2 is

N e g a t iv e R e s i s t a n c e
between 5 to 10K.
R e g io n
C u to ff
r e g io n
VBB

Ve

S a tu r a tio n
r e g io n
R lo a d l in e

Vp

P e a k P o in t

V a ll e y P o i n t
Vv

0 Ip

Iv

Ie

UJT RELAXATION OSCILLATOR

UJT is highly efficient switch. The switching

times is in the range of nanoseconds. Since

UJT exhibits negative resistance
characteristics it can be used as relaxation
oscillator.
C a p a c it o r
V
The circuit diagram
C a is
p a c i t oas
r
with R1
Vshown
+V
d i s c h a r g in g
c h a r g in g
T =R C
V
Vsmall compared to RB1 and
and R2 being
R
V
B UJT.
RB2 Rof
V
E
T =RC
e

BB

BB

VV

Ve

B1

T
R1 v
o

Vo
1

(a )

(b )

SYNCHRONIZED UJT OSCILLATOR

R

+
D1

+
i1

D3

B
V

dc

v
D4

D2
-

E
B

P u ls e T r a n s f
G
C
G
C

1
1
2
2

To S C R
G a te s

DIGITAL FIRING CIRCUIT

A

Pre set
( N n o . o f c o u n tin g b it s )
C lk

F ix e d fr e q u e n c y
O s c i ll a t o r
( f f)

n - b it
C o u n te r

Reset

Load

m ax
m in
En

L o g ic c ir c u it
+
M o d u la to r
+
D r iv e r s t a g e

B
S

F lip - F lo p
(F / F)
R

Reset
fC

Sync
S ig n a l ( ~ 6 V )

ZCD

D .C . 5 V
s u p p ly
A

C a r r ie r
Freq uen cy
O s c i ll a t o r
( 10K H z)

y ( 1 o r 0 )

G1
G2