Chapter 9 Asynchronous

Sequential Logic
9-1 Introduction
9-2 Analysis Procedure
9-3 Circuits With Latches
9-4 Design Procedure

Chapter 9 Asynchronous
Sequential Logic
9-5 Reduction of State and Flow Tables
9-6 Race-Free State Assignment
9-7 Hazards
9-8 Design Example

Unit-5
Synchronous Sequential
Circuits

The change of internal state occurs in response to the

synchronized clock pulse.
Memory elements are clocked flip-flops.

Asynchronous Sequential
Circuits
Since asynchronous circuits dont use clock ,state of
system is allowed to change immediately after input
changesThe change of internal state occurs when
there is a change in the input variables.
Memory elements are unclocked flip-flops or timedelay elements.

9-1 Introduction
Synchronous Sequential
Circuits
Timing problems are eliminated by triggering all
flip-flops with pulse edge.

Asynchronous Sequential
Circuits

Care must be taken to ensure that each new state is

Higher
speed path exists.
stable even though
a feedback
More economical

9-1 Introduction
Asynchronous Sequential
Circuits
When an input variable
changes in value, the y
secondary variables do
not change
instantaneously.

It takes certain time

for the signal to
propogate through
combinational circuit to
Y Excitation Variables.

9-1 Introduction
Asynchronous Sequential
Circuits
In steady-state
condition, the y's
and the Y's are
the same, but
during transition
they are not.

9-1 Introduction
fundamental mode
fundamental mode :Only one input variable can
change at any one time and the time between two
input changes must be longer than the time it
takes the circuit to reach a stable state.

9-2 Analysis
Procedure
Transition Table

Y1 = xy1 + x'y2

Y2 = xy'1 + x'y2

9-2 Analysis
Procedure
Transition Table
(Modified K-mapTake input as columns and secondary variables as rows)

Y1 = xy1 + x'y2

Y2 = xy'1 + x'y2

9-2 Analysis
Procedure
Transition Table
For a state to be stable, the
value of Y must be the same as
that of y = y1y2

9-2 Analysis
Procedure
Transition Table
The Unstable
states, Y y

9-2 Analysis
Procedure
Transition Table
Consider the square for x = 0 and
y = 00. It is stable.
x changes from 0 to 1.
The circuit changes the value of
Y to 01. The state is unstable.
The feedback causes a
change in y to 01. The circuit
reaches stable.

9-2 Analysis
Procedure
Transition Table
In general, if a change in the
input takes the circuit to an
unstable state, y will change until
it reaches a stable state.

9-2 Analysis
Procedure
Flow Table

Flow Table

Transition table whose states

are named by letter symbol
instead of binary values.

9-2 Analysis
Procedure
Flow Table

It is called primitive flow table

because it has only one stable
state in each row.

It is a flow table with more than

one stable state in the same row.

9-2 Analysis
Procedure
Flow Table

9-2 Analysis
Procedure

9-2 Analysis
Procedure
Race Conditions(When unequal delay is encountred
race condition may cause state variable to change in
unpridctable manner

Noncritical Race:
Two or more binary state variables
changefrom
value00in response to a
State variables change
change
in
anainput
variable
to 11. The possible
transition
It is
noncritical
race. The
could be
final stable state that the
00 11
00 01

11

00 10

11

circuit reaches does not

depend on the order in
which the state variables
change.

9-2 Analysis
Procedure
Race Conditions
Critical Race:
State variables change from 00
to 11. The possible transition
could be
It is a critical race. The
00 11
final stable state depends
00 01 11
on the order in which the
state
variables
change.
00 10

An asychronous circuit is described

by the excitation function Y=x1x2+
(x1+x2)y & Output function z=y
a) Draw Logic Diagram of circuit
b) Transition table and Output map
c) Obtain two state flow table.

9-3 Circuits with

Latches
SR Latch
The circuit diagram and truth table of the SR
latch are shown as follows,

9-3 Circuits with

Latches
SR Latch
The circuit diagram of the SR latch can be
redrawn as follows,

9-3 Circuits with

Latches
SR Latch
Y = [(S + y)' + R]'
= (S + y)R' = SR' + R'y
SR' + SR = S ( R' + R ) = S

SR' = S

SR = 0
Y = SR' + R'y = S + R'y when SR=0
Similarly if we use NAND latch which is
reverse of NOR latch the equation will
be Y=S+Ry

9-3 Circuits with

Latches
Analysis Example
Obtain the Boolean equation of
S-R input of latches in circuit

S1 = x1 y2
S2 = x1 x2
R1 = x'1 x'2
R2 = x'2 y1
Then Check whether Condition
SR=0 Satisfied

S1 R1 = x1 y2 x'1 x'2 = 0
S2 R2 = x1 x2 x'2 y1 = 0

9-3 Circuits with

Latches
Y1Analysis
= S1 + R'1y1 = Example
x1y2 + (x1 + x2)y1
Y2 = S2 + R'2y2 = x1x2 + (x2 + y'1)y2

Identify the Critical Race Condition????

9-3 Circuits with

Latches

Latch Excitation
Table
A table that lists the
required inputs S and R
for each of the possible
transitions from y to Y

The first two columns list

the four possible
transitions from y to Y.
The next two columns specify the required input
values that will result in the specified transition.

9-3 Circuits with

Latches
Implementation Example

9-3 Circuits with

Latches
Implementation Example
S = x1x'2

R = x'1
Circuit with
NOR latch

9-4 Design Procedure

Design Procedure
1. Start from Problem Statement by specifying
the problem
2. Design Primitive Flow Table Having only One
Total stable state in a row) From Design
Specification
3. Reduce the flow table by merging rows in
flow table to minimum number of states.
4. Do state assignment
5. Obtain the transition table
6. Finally Draw the logic diagram using SR
latches.(or combination circuit with SR
latches)

9-4 Design Procedure

Design Example(Specification)
Design a gated latch circuit with two inputs G
(gate) and D (data), and one output Q.
1. D input is transferred to Q when G=1
2. Q keeps on changing as per input at D when G=1
3. When G goes to 0 last value of D input is retained
at Q
4. So Gated latch is a memory Element that accepts
value of D when G=1 and Retains values after G
goes to 0.

9-4 Design Procedure

Design Example
Gated-Latch
Design a gated latch circuit with two inputs G (gate)
and D (data), and
one output Q. (In fundamental Mode Two inputs simultenouslyTotal
are not States
allowed to
change)

Inputs
Stat
e
a
b
c
d
e
f

D
0
1
0
1
1
0

G
1
1
0
0
0
0

Output
Q
0(DG=00 to 10 with Q=0)
1(DG=10 to 00 with Q=1)

comments
D =Q because G = 1
D =Q because G = 1

0
1
1

After state c
After state b or f
After state e

After state a or d or starting

9-4 Design Procedure

Design Example
Input Outpu
s
t
Stat
e
D
a
0
b
1
c
0
d
1
e
1
f
0

G
1
1
0
0
0
0

Q
0
1
0
0
1
1

Two of more rows

in the primitive
9-4 Design
Procedure
flow table can be merged into one row
there
are non-conflicting states and
Reduction ifof
the
outputs in each of the columns.
Primitive Flow Table

9-4 Design Procedure

Reduction of the
Primitive Flow Table

9-4 Design Procedure

Transition Table and Logic
Diagram

9-4 Design Procedure

Circuit With SR Latch

9-5 Reduction of State and Flow Tables

Equivalent States
Two states are equivalent if for each possible
input, they give exactly the same output and go to
the same next states or to equivalent next states.
The characteristic of equivalent states is that if
(a,b) imply (c,d) and (c,d) imply (a,b), then both
pairs of states are equivalent.

9-5 Reduction of State and Flow

Tables(Completely specified Table)
Equivalent States: That have same next state and ouptut for every possbile inputs
Implied States:Implication is used to detect indirect equivalance
e.g. when pair of states dont have same next state but have same
output.

Present State N.St(x=0) N.St(x=1) O/P

(x=0) (x=1)
a
d
b
0
0
b
e
a
0
0
c
g
f
0
1
d
a
d
1
0
e
a
d
1
0
f
c
b
0
0
g
a
e
1
0

Implication chart is prepared to detect implied states/Equivalent states.

Vertical/Column naming is done starting from second state.
Horizontal/Row naming is done starting from first state till second last.
Intersection is read from horizontal state to vertical state index.

9-5 Reduction of State and Flow Tables

Without
Implication Table
the first
Example
X 1X 2
00 01
11 10
Sn
A
D/0 D/0 F/0 A/0
B
C/1 D/0 E/1 F/0
C
C/1 D/0 E/1 A/0
D
D/0 B/0 A/0 F/0
E
C/1 F/0 E/1 A/0
F
D/0 D/0 F/0 A/0
G
G/0 G/0 A/0 A/0
H
B/1 D/0 E/1 A/0
S n+1/Zn

B
C AF
D

BD
AF

Without
the last

DF

E
AF DF
F BD

DG
AF

H
A

BG
AF

BC
B C D

BC
AF

BC
DF

DG
AF

9-5 Reduction of State and Flow Tables

Implied Pairs
B

example
X 1X 2

Sn
A
B
C
D
E
F
G
H

00
D/0
C/1
C/1
D/0
C/1
D/0
G/0
B/1

01
11
D/0 F/0
D/0 E/1
D/0 E/1
B/0 A/0
F/0 E/1
D/0 A/0
G/0 A/0
D/0 E/1
S n+1/Zn

10
A/0
F/0
A/0
F/0
A/0
F/0
A/0
A/0

C AF
D

BD
AF

DG
AF

DF
DF

E
AF
F BD

H
A

BG
AF

BC
B C D

BC
AF

BC
DF

DG
AF

9-5 Reduction of State and Flow Tables

The equivalent states [A F] [B H] [B C] [C H]

Denoted by B
Denoted
by
A
The largest group of
B
Combined
equivalent states
into

C
AF
[A F], [B C H],
[B,C,H]
[D], [E], [G]
D BD

AF
X 1X 2
DF
DF

00 01
11 10 E
AF
Sn
A
D/0 D/0 A/0 A/0 F BD
B
C/1 D/0 E/1 A/0
BG
DG
DG
G

AF
AF
AF
D
D/0 B/0 A/0 A/0
E
B/1 A/0 E/1 A/0 H BC BC BC
AF
DF
G
G/0 G/0 A/0 A/0
A B C D E F G
S n+1/Zn

Procedure for Merging Flow

Table(Incompletely Specified State Table)
Determine all compatible pairs in primitive
flow table using Implication table
( Two states are Compatible if for Each possible input , they have same
output whenever it is specified and have same next state whenever it is
specified.)

Find the maximal compatibles with help of

merger diagram.
Find a minimal collection of compatibles
that covers all the states and is closed.

Example
Draw implication chart?

Merger Diagram for maximal

Compatibles

Compatible pairs derived from implication chart which are

checked in implication chart
( a,b)(a,c)(a,d)(b,e)(b,f)(c,d)(e,f)

Now Find Maximal Compatibles by Merger Diagram

1.
Is group of compatibles that contain all possible compatible states
2.
In merger diagram each state is represented by a single dot.
3.
Compatible pair is represented by a line between dots.
4.
After connecting all the states identify the single dots OR Lines
OR Triangles OR polygons with each diagonal connected.
These represent the maximal compatibal pairs.
In this example these are (a,b) (a,c,d) & (b,e,f)

Last step. Closed Covering

Condition
Set of chosen compatibles must cover all the
states of original state table.
Closure condition states that there should be no
implied states of chosen set OR if taken implied
states should be included within the set selected.
From Last example if select (a,c,d) & (b,e,f)
Covering condition is satisfied?
Closed covering is satisfied?
So we can leave the (a,b) maximal compatible while
reducing the flow table.

 Assume that compatible pairs derived from implication table

of any flow table are
(a,b),(a,d),(b,c),(c,d),(c,e)(d,e) also given that implied states of
(a,b)imply(b,c),
(a,d)imply (b,c) ,
(b,c)imply(d,e),
(c,d)imply(a,d),
(d,e)imply(b,c)
a) Determine maximal Compatible & what pairs should be
chosen out of maximal compatibles such that they satisfies
closure property & Covering Condition

9-6 Race-Free State Assignment

The primary objective in choosing a proper
binary state assignment is the prevention of
critical races.
Critical races can be avoided by making a binary
state assignment in such a way that only one
variable changes at any given time when a state
transition occurs in the flow table.

9-6 Race-Free State Assignment

Three-Row Flow-Table Example
00
01
11

This assignment will cause

a critical race during the
transition from a to c.

9-6 Race-Free State Assignment

Three-Row Flow-Table Example
00
01
11
10

The transition from a to c

must now go through d,
thus avoiding a critical race.

9-6 Race-Free State Assignment

Multiple-Row Method
In the multiple-row assignment, each state in the
original flow table is replaced by two or more
combinations of state variables.
Note that a2 is
adjacent to d2, c1,
b2.

9-6 Race-Free State Assignment

Multiple-Row Method

The original
flow table

HAZARDS
In designing Asynch Circuits, to ensure their
proper operation, certain restricting and
precautions need to taken:
Need to operate in Fundamental mode.
Must be free of critical races.
A phenomena known as Hazard
( unwanted switching transients) that may
cause circuit to malfunction needs to taken
care. This happens due to different
propagation delays in different paths of in
the circuit.

Hazards in combinational circuits.

Y=x1x2 + x2x3

Y= x1x2 + x2x3

Y=(x1+x2) (x2+x3)

HAZARDS IN SEQUENTIAL CIRCUITS

A momentary incorrect signal fed back in an asynchronous circuit may cause circuit to go into a wrong stable state.
1.
Assume that the circuit is in total stable state yx1x2 111 and x2 changes from 1 0 Next total stable state
should be 110.
2.
Because of hazard output may go to 0
3.
Which when fed to circuit s gate 2 it keeps the output of gate 2 to zero which is expected to be 1 leading to
wrong total stable state 010
4.
This hazard can also be eliminated by adding extra gate.

Implementation with SR Latch.

To avoid static hazards in Asych Seq circuits, designing with SR Latch
provide the solution.
A momentary 0 signal applied to S or R i/p of NOR Latch will have no
effect on the state of the circuit.
Similarly a momentary 1 signal applied to S or R i/p of NAND Latch
will have no effect on the state of the circuit.

S = (AB + CD)
R = (AC)
Q = (QS)
= [Q(AB)(CD)]
Refer Fig b.
Let Q =1 then Q=0
Q will be maintained at
1 even if other two i/p
go momentarily to 1.
Asynchromous Seq
Circuits constructed
this way can avoid
the static 1 hazards.

Essential Hazards
This type of hazard is caused by unequal delays
along two or more paths that originate from the
same input.
Essential hazards cant be corrected by adding
redundant gates as in static hazards. This can be
corrected by adjusting the amount of delay in the
affected path.
To avoid essential hazards, each feedback loop
must be handled with individual care to ensure
that the delay in the FB path is long enough
compared with the delays of other signals that
originate from the i/p.

Thanks
All the Best

for
PUE & University Examination