Phase Lock Loop

Applications

PLL Applications

FM Demodulation

Phase-Locked Loop Based Clock

Generator
PLL perform:

Clock input division

Frequency Multiplication
In this manner, the non integer frequencies can be developed.

Integer-N Frequency Synthesizers without Prescalers

Divider /R

Frequency synthesizers are found in FM receivers, CB transceivers,

TV receivers, etc. In these applications, there is a need for
generating a great number of frequencies with a narrow spacing of
50, 25, 10, 5, or even 1 kHz. If channel spacing of 10 KHz is
desired, a reference frequency of 10 KHz is normally chosen. A
quartz crystal oscillating in kHz region is quite bulky and not
practical. A more convenient to use higher frequency crystal in the
range of MHz and scale down to desired reference frequency. This

Integer-N Frequency Synthesizers with Prescalers cont.

Divider /R
fosc = 10MHz

Four-modulus prescalers
To extend the upper frequency range of a frequency synthesizer
but still allows the synthesis of lower frequencies. The solution is
the four-modulus prescaler. The four-modulus prescaler is a
logical extension of the dual-modulus prescaler. It offers four
different scaling factors, and two control signals are required to
select one of the four available scaling factors.

Integer-N Frequency Synthesizers with Prescalers cont.

As an example, the four-modulus prescaler can divide by factors of 100, 101, 110, and
111. By definition, it scales down by 100 when both control inputs are LOW. The internal
logic of the four-modulus prescaler is designed so that the scaling factor is increased by
1 when one of the control signals is HIGH, or increased by 10 when the other control
signal is HIGH. If both control signals are HIGH, the scaling factor is increased by 1 + 10
= 11.
There are three programmable /N counters in the system: /N1, /N2, and /N3 dividers. The
overall division ratio is given by:
Ntot = 100N1 + 10N2 + N3
In this equation N3 represents the units, N2 the tens, and N1 the hundreds of
the division ratio Ntot. Here N2 and N3 must be in the range 0 to 9, and N1 must be at least
as large as both N2 and N3 because when the content of N1 becomes 0, all /N1, /N2
and /N3 counters are reloaded to their preset values, and the cycle is repeated (N 1,min =
9). The smallest realizable division ratio is consequently:
Ntot,min = 100 x 9 = 900
For a reference frequency f1 of 10 kHz, the lowest frequency to be synthesized is
therefore: 900 x f1 = 9 MHz.

Integer-N Frequency Synthesizers Examples

Numerical Example: We wish to generate a frequency that is 1023 times the
reference frequency. The division ratio Ntot is thus 1023; hence N1 = 10, N2 = 2,
and N3 = 3 are chosen. Furthermore, we assume that the /N1 counter has just
stepped down to 0, so all three counters are now loaded to their preset values.
Both outputs of the /N2 and /N3 counters are now HIGH, a condition that causes
the four-modulus prescaler to divide initially by 111.
Solution: After N2 x 111 = 2 x 111 = 222 pulses generated by the VCO, the /N 2
counter steps down to 0. Consequently, the prescaler will divide by 101. At this
moment, the content of the /N3 counter is 3 2 = 1. After another 101 pulses
(1 x 101) have been generated by the VCO, the /N3 counter also steps down to 0.
The division ratio of the four-modulus prescaler is now 100.
The content of the /N1 counter is now 7. After another 700 pulses (7 x 100) have
been generated by the VCO, the /N1 counter also steps down to 0, and the cycle is
repeated. To step through an entire cycle, the VCO had to produce a total of
Ntot = 2 x 111 + 1 x 101 + 7 x 100 = 1023 pulses, which is exactly the
number desired.

Jitters Example

Clock Data Recovery

The first CDR design required that the same clock used to serialize the
data be sent to the receiver alongside the data. This method created
some added problems for the receiver, as it had to deal with the jitter in
the data stream and with the jitter in the clock stream, alongside the data
stream. Another issue is the amount of data links is reduced by two using
this system.

Differentiation CDR
The steps taken by the algorithm to obtain the recovered data. The first plot is
the input data, the second is the differentiated input data. We can see that the
peaks occur at the zero crossings of the input data. The third plot is the fullwave
rectified differentiated data. This data is used to create a clock, which is then
used to create the fourth plot, the regenerated data

Clock Data Recovery

To counteract the effect of the system described earlier, a method
utilizing two separate clock was developed. The transmitter serializes the
data stream using the clock A. The cdr, at the receiver, uses information
from a reference clock, clock B, located at the receiver end. To
accomplish this operation a Phase-Locked Loop (PLL) is used.

Integer-N Frequency Synthesizers with Prescalers

Fixed division ratio prescalers:

To generate higher frequencies, prescalers are used; these are
often built with
other IC technologies such as ECL, Schottky TTL, GaAs (galliumarsenide), or
SiGe (silicon-germanium compound). Such prescalers extend the
range of frequencies into the microwave frequency bands. This
implies that it is no longer possible to generate every desired
integer multiple of the reference frequency f1; if V = 10, only

Integer-N Frequency Synthesizers with Prescalers cont.

Dual-modulus prescalers
A counter whose division ratio can be switched from one value to another by an
external control signal. As an example, the prescaler above can divide by a factor of
11 when the applied control signal is HIGH, or by a factor of 10 when the control
signal is LOW. It can be demonstrated that the dual-modulus prescaler makes it
possible to generate a number of output frequencies that are spaced only by f1 and
not by a multiple of f1.

Integer-N Frequency Synthesizers with Prescalers cont.

The following conventions are used with respect to dual-modulus
prescalers:
Both programmable /N1 and /N2 counters are DOWN counters.
The output signal of both of these counters is HIGH if the
content of the corresponding counters has not yet reached the
value 0.
When the /N1 counter has counted down to 0, its output goes
LOW and it
immediately loads both counters to their preset values N1 and
N2, respectively.
N1 is always greater than or equal to N2.
As shown by the AND gate, underflow below 0 is inhibited in
the case of the /N2 counter. If this counter has counted down to
0, further counting pulses are inhibited.

Integer-N Frequency Synthesizers with Prescalers cont.

The operation of the system becomes clearer if we assume that
the /N1 counter has just counted down to 0 and both counters
have been loaded with their preset values N1 and N2, respectively.
We now have to find the number of cycles the VCO must produce
until the same logic state is reached again. This number is the
overall scaling factor Ntot of the arrangement shown in Fig. 6.4. As
long as the /N2 counter has not yet counted down to 0, the
prescaler is dividing by V + 1. Consequently, both the /N1 and
the /N2 counters will step down by one count when the VCO has
generated V + 1 pulses. The /N2 counter will therefore step down
to 0 when the VCO has generated N2 x (V + 1) pulses. At that
moment, the /N1 counter has stepped down by N2 countsthat is,
its content is N1 N2.
The scaling factor of the dual-modulus prescaler is now switched to
the value
V. The VCO will have to generate additional (N1 - N2)V pulses until
the /N1
counter steps to 0. When the content of N1 becomes 0, both the

Integer-N Frequency Synthesizers Examples

If V = 10, Ntot = 10N1 + N2
In this expression, N2 represents the units and N1 the tens of the
overall division ratio Ntot. Then N2 must be in the range of 0 9,
and N1 can assume any value greater than or equal to 9that is,
N1,min = 9. The smallest realizable
division ratio is therefore: Ntot,min = N1,minV = 90
The synthesizer is thus able to generate all integer multiples of
the reference frequency f1 starting from Ntot = 90.
If V = 16, Ntot = 16N1 + N2, Then N2 range of 0 15 N1,min = 15.
In this case, the smallest realizable division ratio N tot,min = 16 x 15
= 240.
Using V = 100, Ntot = 100N1 + N2
where N2 range of 0 99 N1,min = 99.
In this case, the smallest division ratio Ntot,min = 100N1,min = 100 x
99 = 9900
If the reference frequency f1 = 10 kHz, the lowest frequency to be

References:
http://www.scribd.com/doc/237983665/PLL
http://www.delroy.com/PLL_dir/tutorial/PLL_tutorial_slides.pdf
Phase Locked Loops 6/e, 6th Edition by Roland Best
https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF8#q=an535
http://eprints.lancs.ac.uk/52334/1/PLLbook_chapter_final_2.pdf
http://www.ti.com/lit/ds/symlink/lm565.pdf
PLL-74HC4046_Application_Note%20(1).pdf
http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L170-FreqSy
n-I(2UP).pdf
http://iris.lib.neu.edu/cgi/viewcontent.cgi?article=1007&context=elec_comp_theses

References:
http://www.scribd.com/doc/237983665/PLL
http://www.seas.ucla.edu/brweb/teaching/215C_W2013/PLLs.pdf
http://www.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf
http://www.ti.com/lit/an/snoa351/snoa351.pdf
http://memo.cgu.edu.tw/jtkuo/files/eelab%202014%28III%29/1230_Lab1
2_Expxx_PhaseLockedLoop.pdf
http://siihr64.iihr.uiowa.edu/MyWeb/Teaching/ece_55141_2013/Homewor
k/HomeworkAssignment08Solution.pdf
http://www.freeclassnotesonline.com/VCO-and-PLL-Calculations-HW.php
http://ecee.colorado.edu/~ecen4618/lab4.pdf