Documente Academic
Documente Profesional
Documente Cultură
Vacuum Tube
Generations of Computers
Vacuum tube - 1946-1957 (One bit Size of a hand)
Transistor - 1958-1964 (One bit Size of a fingernail)
Small scale integration - 1965 on
Up to 100 devices on a chip
Thousands of bits
on the size of a
hand
Millions of bits
on the size of a
fingernail.
Introduction
Computer architecture is defined by computer structure and
behavior as seen by their programmer that uses machine
language instructions.
This includes the instruction formats, addressing modes,
instruction set and general organization of the CPU registers
Organization of Von-Neumann
Machine (IAS Computer)
The task of entering and altering programs for
ENIAC was extremely tedious
Stored program concept says that the program is
stored in the computer along with any relevant data
A stored program computer consists of a processing
unit and an attached memory system.
The processing unit consists of data-path and
control. The data-path contains registers to hold
data and functional units, such as arithmetic logic
units and shifters, to operate on data.
AC
MQ
MBR
IBR
PC
IR
MAR
Example of an Instruction-pair.
Load M(100), Add M(101)
0000000100011111010000000101000111110101
ACAC= 7
3
MEMORY
1. LOAD M(X) 500, ADD M(X) 501
2. STOR M(X) 500, (Other Ins)
.....
500. 3
501. 4
PC
21
MAR
501
500
21
MBR LOAD
STOR
M(X)
M(X)500,
500,
43 ADD
(Other
M(X)
Ins)501
IR
LOAD
STOR
ADD M(X)
M(X)
IBR
ADD
(Other
M(X)
Ins)
501
AC
37
MQ
500
LOAD
M(X)
MBR
MBR
=500
4
3
ADD
M(X)
501
(OtherSTOR
Ins) M(X)
501
IBR
Add
M(X)
PC
==PC
12
Mar
PC
MAR
PC
IR
MAR
MAR==500
=500
12
501
MAR
MAR
add== 501
add == 500
add
add =12
Instruction Format
INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field
- specifies the way the operand or the
effective address is determined
The number of address fields in the instruction format
depends on the internal organization of CPU
- The three most common CPU organizations:
Single accumulator organization:
ADD X
/* AC AC + M[X] */
General register organization:
ADD R1, R2, R3
/* R1 R2 + R3 */
ADD R1, R2
/* R1 R1 + R2 */
MOV
R1, R2
/* R1 R2 */
ADD R1, X
/* R1 R1 + M[X] */
Stack organization:
PUSH
X
/* TOS M[X] */
ADD
Three-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B
/* R1 M[A] + M[B] */
ADD R2, C, D
/* R2 M[C] + M[D] */
MUL
X, R1, R2
/* M[X] R1 * R2
- Results in short programs
- Instruction becomes long (many bits)
Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :
MOV
ADD
MOV
ADD
MUL
MOV
R1, A
R1, B
R2, C
R2, D
R1, R2
X, R1
/* R1 M[A]
*/
/* R1 R1 + M[B] */
/* R2 M[C]
*/
/* R2 R2 + M[D] */
/* R1 R1 * R2
*/
/* M[X] R1
*/
*/
Zero-Address Instructions:
A
B
C
D
X
/*
/*
/*
/*
/*
/*
/*
/*
TOS A
*/
TOS B
*/
TOS (A + B)
*/
TOS C
*/
TOS D
*/
TOS (C + D)
*/
TOS (C + D) * (A + B) */
M[X] TOS
*/
ADDRESSING MODES
Addressing Modes:
* Specifies a rule for interpreting or modifying the
address field of the instruction (before the operand
is actually referenced)
* Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the
instruction efficiently
Implied
Immediate
Register
Register Indirect
Auto Increment or Auto Decrement
Direct
Indirect
Relative
Index
Base Register
Register Address mode:Operand are in registers that reside within the CPU.
Ex: MOV R1,R2
Register Indirect address:In the mode the inst specifies a register in the CPU whose
content give the address of the operand in memory.
Eg: MOV R1,(R2)
Auto increment or Auto decrement: Similar to register indirect mode except that the register is
incremented or decrement after its value is used to access
memory.
2 forms post and pre : Mov R1,(R2)+ post increment
Mov R1,+(R2) pre increment
Mov R1,(R2)- post decrement
Mov R1,-(R2) post decrement
200
201
202
Memory
Load to AC Mode
Address = 500
Next instruction
R1 = 400
XR = 100
399
400
450
700
500
800
600
900
702
325
800
300
AC
Addressing
Effective
Mode
Address
Direct address 500 /* AC (500)
*/
800
Immediate operand
/* AC 500
*/
Indirect address
800 /* AC ((500)) */
Relative address
702 /* AC (PC+500)
Indexed address
600 /* AC (XR+500)
Register
/* AC R1
*/
Register indirect
400
/* AC (R1) */
Autoincrement 400 /* AC (R1)+
*/
700
Autodecrement 399 /* AC -(R)
*/
450
Content
of AC
500
300
*/
325
*/
900
400
700
Instruction types
Mnemonic
INC
DEC
ADD
SUB
MUL
DIV
ADDC
SUBB
NEG
Shift Instructions
Name
Logical shift right
Logical shift left
Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Rotate right thru carry
Rotate left thru carry
Mnemonic
SHR
SHL
SHRA
SHLA
ROR
ROL
RORC
ROLC
Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save address
Continue Tracing
Void student1()
{
say nursery rhyme;
Write Computer Architecture;
call student2;
Write your School name;
}
Continue Tracing
Void student2()
{
act like vegetable vendor;
Write B1 slot;
call student3;
Write your branch;
}
Continue Tracing
Void student3()
{
Sing a song;
Write your name;
}
Subroutine call
CALL
SP SP 1 decrement SP
M[SP] PC Push content of PC into stack
PC Effective Address (EA) Transfer control to subroutine.
RTN
PC M[SP] POP stack and transfer to PC.
SP SP + 1 Inc SP
Recursive subroutine is a subroutine that calls itself.
Recursive subroutines
Subroutine that calls itself
If only one register or memory location is
used to hold the return address, when
subroutine is called recursively, it destroys
the previous return address.
So, stack is the good solution for this
problem
Cont..
2. Processor I/O:
Data may be transferred to or from a
peripheral device by transferring between
the processor and I/O module.
3. Data processing:
The processor may perform some
arithmetic or logic operation on data.
4. control:
An instruction may specify the sequence
of execution be altered.
Start
Fetch next
instruction
Execute cycle
Execute
instruction
Halt
1. Instruction format
15
Opcode
Address
0 3 4
2.Integer format
Magnitude
S 1
15
Cont..
3. Internal CPU registers:
Program counter(PC)- Address of
instruction
Instruction Register (IR)- Instruction being
executed
Accumulator(AC)- Temporary register.
Partial list of opcodes:
0001- Load AC from memory
0010- Store AC from memory
0101- Add to AC from memory
Program interrupt
Program interrupt refers to transfer of program ctrl from
currently running program to another service program as a
result of external or internal generated request.
Interrupt is usually initiated by an internal or external signal
rather from execution of inst.
Address of ISR (Interrupt Service Routine) is determined by
H/W rather from address field.
Cont..
PSW (program status word)
Collection of all status bit conditions in the
CPU is called PSW.
It is a hardware register and contains status
information that characterizes state of CPU.
PROGRAM INTERRUPT
Types of Interrupts:
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure
Internal interrupts (trap)
Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer
Hardware.
Software Interrupts are initiated by executing an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor
mode
-> Allows to execute a certain class of operations
which
are not allowed in the user mode
Cont..
An m- bit register is an ordered set of m
flip flops designed to store m word. (z0
zm-1)
Each bit is stored in separate flip flops.
All flip flops have common control line.(clk,
clear)
Registers can be made up of various flip
flops.
diagram
Cont
Register z reads in the data word x each
time it is clocked. To maintain the contents
of z constant, z inputs bus should be
enabled always.
Parallel load: diagram
introduce a control line load, which causes
the register to read in the current value of x
when it is clocked and load=1, if load=0 the
previous value is retained in the register.
Shift register
Transfer the contents into and from register
1bit at a time.
M- bit shift register consists of m flip flops
each of which is connected to its left or right
neighbor.
Data can be entered 1 bit at a time at one end
of register and can be removed 1 bit at a time
from the other end known as serial i/p o/p.
diagram
Cont..
Right shift is accomplished by activating
the shift enable line connected to the clk
input of each flip flop.
Right shift operation changes the registers
state as,
(Xzm-1 zm-2z1):=(zm-1 zm-2,.z1,z0)
Left shift operation changes the register
state as (zm-2 zm-3z0,x):=(zm-1 zm-2,
.z1,z0)
Register files
Set of general purpose registers r0:rm-1
known as register file RF.
Each register Ri is individually
addressable.
Arithmetic logic instruction take two ,three
address format.
R2=f(R1,R2)- 2 address
R3=f(R1,R2)- 3 address
Cont..
Intermediate results are stored in
processor with the help of register.
RF functions as a RAM.
RF differs from M becomes RF requires 2
or more operands accessed
simultaneously.
RF is also known as multiport RAM
Address C
Data in C
16
Port C
Register File
RF
Address A
Port A
16
Data out A
Port B
16
Data out B
Address B
Data in C
16
11
Write
address C
2
S
16
16-bit register R3
4-way 16-bit
demultiplexer
16
16-bit register R2
16
16
16-bit
register R1
0101
16
16
16-bit register R0
16
16
01
Read
address A
4-way 16-bit
multiplexer
16
Data out A
4-way 16-bit
multiplexer
16
Data out B
2
Read
address B