WATCHDOG TIMER

A watchdog timer (WDT or sometimes

called a computer operating properly or
cop timer , or simply called watchdog )
Itis an electronictimer that is used to
detect
and
recover
from
computer
malfunctions.
During normal operation, the computer
regularly restarts the watchdog timer to
prevent it from elapsing, or "timing out". If,
due to a hardware fault or program error,
the computer fails to restart the watchdog

FEATURES
Debug mode
Enabled by software but requires a hardware
reset or watchdog reset/interrupt to be
disabled
Incorrect/incomplete feed sequence causes
reset/interrupt is enabled
Flag to indicate watchdog reset
Programmable 32-bit timer with internal pre
scalar
Internally resets chip if not periodically
reloaded

TIMER/COUNTER

DESCRIPTION
The Timer/Counter is designed to count
cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally
generate interrupts or perform other actions
at specified timer values, based on four
match registers. It also includes four capture
inputs to trap the timer value when an input
signal transitions, optionally generating an
interrupt.

FEATURES
A 32-bit Timer/Counter with a
programmable 32-bit Prescaler.
Counter or Timer operation
Up to four 32-bit capture channels per
timer, that can take a snapshot of the timer
value when an input signal transitions.
A capture event may also optionally
generate
an interrupt.

 Four 32-bit match registers that allow:

Continuous operation with optional interrupt
generation on match.
Stop timer on match with optional interrupt
generation.
Reset timer on match with optional interrupt
generation.
Up to four external outputs corresponding to
match registers, with the following capabilities:
Set low on match.
Set high on match.
Toggle on match.
Do nothing on match.

Counter/timer hardware is a crucial

component of most embedded
systems.
In some cases, a timer measures
elapsed time (counting processor
clock ticks).
In others, we want to count or time
external events. The names counter
and timer can be used
interchangeably when talking about
the hardware.
The difference in terminology has
more to do with how the hardware is

Asimple timer similiar to those often

included on-chip within a
microcontroller. You could build
something similar from a couple of
74HC161 counters or a
programmable logic device.
The timer shown consists of a
loadable 8-bit count register, an
input clock signal, and an output
signal.
Software loads the count register
with an initial value between 0x00
and 0xFF

. To restart the timer, software reloads

the count register with the same or a
different initial value.
If a counter is an up counter, it
counts up from the initial value
toward 0xFF. A down counter counts
down, toward 0x00.
A typical counter will have some
means to start the counter running
once it is loaded, usually by setting a
bit in a control register.

INTERRUPTS
An interrupt is an event which stops
the master processor executing its
current instruction and handling the
interrupt with a predefined handling
mechanism Of course this can happen
asynchronously, therefore it has to be
defined how the master processor
communicates with the I/O devices.
(e.g. IfanI/Ointerrupt-handlercan be
interrupted by another I/O device)

Interrupts are the common way of I/O

devices
communicating
with
the
processing unit. There are other ways like
polling or memory mapping
INTERRUPT LATENCY :The amount of
time between the assertion of an interrupt
signal and the start of the associated
interrupt service routine. Factors that
affect interrupt latency include the length
of time that interrupts are disabled during
normal program execution, processor
speed, and preemption of the processor
by higher priority interrupts.

 INTERRUPT SERVICE ROUTINE: A small

piece of software executed in response to
a particular interrupt. Abbreviated ISR.
INTERRUPT TYPE: A unique number
associated with each interrupt. The
interrupt type is typically the processor's
index into the interrupt vector.
INTERRUPT VECTOR :The address of an
interrupt service routine . This term is
sometimes used incorrectly to refer to
either the interrupt type or the address of
the interrupt vector.

VECTOR INTERRUPTS
This is the fastest system
The onus is placed on the requesting device to
request the interrupt, and identify itself.
The identity could be a branching address for the
desired interrupt-handling routine.
If the device just supplies an identification
number, this can be used in conjunction with a
lookup table to determine the address of the
required service routine.
Response time is best when the device requesting
service also supplies a branching address.

DISADVANTAGES
The extra chip required
Resultant increases in cost
More board space and power
consumption
Fixed priority in hardware.