MOSFET PSPICE Circuits

-1 .0 0 0 V 4 .2 2 5 u A
R 1
-1 .0 0 0 V
1
I
-1 .0 0 0 V -1 .0 0 0 V

1Vdc
M 4 -4 .2 2 5 u A
V1 4 .2 2 5 u A
0A
0A
V2 -6 5 0 .0 m V M b re a k P 4 . 21 2. 05 u1 A0 p A
-0 .6 5 0 V d c
0
0
0V

0
0

Current-Voltage Characteristics - PSPICE 1

 MOSFET PSPICE Circuits:
Id vs Vsd
Drain current at different gate voltages Current-Voltage
7.0 10
-5
Characteristics -
6.0 10
-5 PSPICE
I_-0.55V
-5
5.0 10 I_-0.75V
I_-1.25V
I_-2.5V
-5
4.0 10 I_-1.75V
I (A)
D

-5
3.0 10

-5
2.0 10

-5
1.0 10

0
0.0 10
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2
2
V (V)
SD
 MOSFET Sub-threshold
Voltage Slope: Id vs Vg
Sub-threshold characteristics of a MOSFET:
exponential dependence ID ~ exp (VG/kT).
Vsub.slope = 60 mV.
Vap 2
I2 I S exp nk BT
ln ln ln10
I1 Vap1
I S exp
nk BT
Vap 2 Vap1
2.3; for n 1
nk BT
V Vap 2 Vap1 2.3 0.026
0.060[V ]
3
MOSFET PSPICE Circuits:
Id vs Vg

Sub-threshold
Regime -
Drain Current vs
Gate Voltage
(MultiSim)

n=1;
Vst = 0.06 V

4
MOSFET PSPICE Circuits:
Id vs Vg

Sub-threshold
Regime -
Drain Current vs
Gate Voltage
(MultiSim)

n=1;
Vst = 0.06 V

5
 MOSFET Symbols

Schematics and circuit symbols 6

 More MOSFET Symbols

Schematic structure of n-channel MOSFET (NMOS) (a) and circuit

symbols for MOSFET (b), n-channel MOSFET (c), and n-channel
MOSFET when the bulk (substrate) potential has to be specified in a
7
circuit (d).
 MOSFET Model: A Voltage
Controlled Resistor

Including the effect of channel-length

modulation modeled by output
resistance ro = |VA|/ID.
8
 MOSFET and CMOS

Cross section of a CMOS integrated circuit. Note that the

PMOS transistor is formed in a separate n-type region, known
as an n well. Another arrangement is also possible in which
an n-type body is used and the n device is formed in a p well. 9
 CMOS Circuits:
a MOSFET Amplifier

10
 CMOS Circuits:
MOSFET Current Mirror

Output characteristic of the current mirror Q2 is

matched to Q1. 11
CMOS Circuits: A Common-Source
Amplifier

12
CMOS Circuits: a Common-gate
Amplifier

13
 CMOS Circuits:
The CMOS Inverter

14